| Commit message (Collapse) | Author | Age | Files | Lines | |
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| * | xilinx: Add tristate buffer mapping. (#1528) | Marcin Kościelnicki | 2019-12-04 | 1 | -9/+8 |
| | | | | Fixes #1225. | ||||
| * | synth_xilinx: Merge blackbox primitive libraries. | Marcin Kościelnicki | 2019-11-06 | 1 | -22/+3 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | First, there are no longer separate cell libraries for xc6s/xc7/xcu. Manually instantiating a primitive for a "wrong" family will result in yosys passing it straight through to the output, and it will be either upgraded or rejected by the P&R tool. Second, the blackbox library is expanded to cover many more families: everything from Spartan 3 up is included. Primitives for Virtex and Virtex 2 are listed in the Python file as well if we ever want to include them, but that would require having two different ISE versions (10.1 and 14.7) available when running cells_xtra.py, and so is probably more trouble than it's worth. Third, the blockram blackboxes are no longer in separate files — there is no practical reason to do so (from synthesis PoV, they are no different from any other cells_xtra blackbox), and they needlessly complicated the flow (among other things, merging them allows the user to use eg. Series 7 primitives and have them auto-upgraded to Ultrascale). Last, since xc5v logic synthesis appears to work reasonably well (the only major problem is lack of blockram inference support), xc5v is now an accepted setting for the -family option. | ||||
| * | xilinx: Add URAM288 mapping for xcup | David Shah | 2019-10-23 | 1 | -1/+23 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | xilinx: Add support for UltraScale[+] BRAM mapping | David Shah | 2019-10-23 | 1 | -1/+6 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | xilinx: Support multiplier mapping for all families. | Marcin Kościelnicki | 2019-10-22 | 1 | -8/+45 |
| | | | | | | This supports several older families that are not yet supported for actual logic synthesis — the intention is to add them soon. | ||||
| * | Call memory_dff before DSP mapping to reserve registers (fixes #1447) | N. Engelhardt | 2019-10-17 | 1 | -0/+1 |
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| * | Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9 | Eddie Hung | 2019-10-08 | 1 | -7/+8 |
| |\ | | | | | Rename abc_* names/attributes to more precisely be abc9_* | ||||
| | * | Merge branch 'master' into eddie/abc_to_abc9 | Eddie Hung | 2019-10-04 | 1 | -3/+7 |
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| | * | | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 1 | -6/+7 |
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| * | | | Add comment on why partial multipliers are 18x18 | Eddie Hung | 2019-10-04 | 1 | -4/+8 |
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| * | | | Fix typo in check_label() | Eddie Hung | 2019-10-04 | 1 | -1/+1 |
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| * | | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9` | Eddie Hung | 2019-10-04 | 1 | -2/+6 |
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| * | Merge pull request #1359 from YosysHQ/xc7dsp | Eddie Hung | 2019-09-29 | 1 | -4/+32 |
| |\ | | | | | DSP inference for Xilinx (improved for ice40, initial support for ecp5) | ||||
| | * | Re-order | Eddie Hung | 2019-09-27 | 1 | -1/+1 |
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| | * | Typo | Eddie Hung | 2019-09-26 | 1 | -1/+1 |
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| | * | select once | Eddie Hung | 2019-09-26 | 1 | -3/+5 |
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| | * | Stop trying to be too smart by prematurely optimising | Eddie Hung | 2019-09-26 | 1 | -1/+3 |
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| | * | Call 'wreduce' after mul2dsp to avoid unextend() | Eddie Hung | 2019-09-25 | 1 | -0/+1 |
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| | * | Revert "Add a xilinx_finalise pass" | Eddie Hung | 2019-09-23 | 1 | -2/+0 |
| | | | | | | | | | This reverts commit 23d90e0439ffef510632ce45a3d2aff1c129f405. | ||||
| | * | Add a xilinx_finalise pass | Eddie Hung | 2019-09-23 | 1 | -0/+2 |
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| | * | Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40 | Eddie Hung | 2019-09-20 | 1 | -1/+1 |
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| | * | Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp | Eddie Hung | 2019-09-19 | 1 | -1/+3 |
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| | * | | synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2 | Eddie Hung | 2019-09-19 | 1 | -1/+4 |
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| | * | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-18 | 1 | -6/+15 |
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| | * | | | Missing space | Eddie Hung | 2019-09-11 | 1 | -0/+1 |
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| | * | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-11 | 1 | -10/+13 |
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| | * | | | | Move "(skip if -nodsp)" message to label | Eddie Hung | 2019-09-10 | 1 | -4/+4 |
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| | * | | | | Really get rid of 'opt_expr -fine' by being explicit | Eddie Hung | 2019-09-10 | 1 | -3/+0 |
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| | * | | | | Remove wreduce call | Eddie Hung | 2019-09-10 | 1 | -1/+0 |
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| | * | | | | Add comment for why opt_expr is necessary | Eddie Hung | 2019-09-10 | 1 | -0/+2 |
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| | * | | | | Revert "Remove "opt_expr -fine" call" | Eddie Hung | 2019-09-10 | 1 | -0/+1 |
| | | | | | | | | | | | | | | | | | | | | | This reverts commit bfda921d0317bfb4cb6fc9de8a556c2258b709bc. | ||||
| | * | | | | Rename label to map_dsp | Eddie Hung | 2019-09-10 | 1 | -1/+1 |
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| | * | | | | Remove "opt_expr -fine" call | Eddie Hung | 2019-09-10 | 1 | -1/+0 |
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| | * | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-05 | 1 | -9/+12 |
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| | * \ \ \ \ | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-30 | 1 | -14/+23 |
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| | * \ \ \ \ \ | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-08-30 | 1 | -1/+52 |
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| | | * \ \ \ \ \ | Merge branch 'master' into xc7dsp | David Shah | 2019-08-30 | 1 | -13/+68 |
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| | * | \ \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-20 | 1 | -14/+17 |
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| | * \ \ \ \ \ \ \ \ | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-08-15 | 1 | -1/+5 |
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| | | * | | | | | | | | xilinx: Rework labels for faster Verilator testing | David Shah | 2019-08-13 | 1 | -1/+5 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | * | | | | | | | | | Add DSP_A_MAXWIDTH_PARTIAL, refactor | Eddie Hung | 2019-08-13 | 1 | -1/+1 |
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| | * | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-12 | 1 | -1/+1 |
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| | * | | | | | | | | | Pack partial-product adder DSP48E1 packing | Eddie Hung | 2019-08-09 | 1 | -0/+2 |
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| | * | | | | | | | | | Combine techmap calls | Eddie Hung | 2019-08-08 | 1 | -2/+1 |
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| | * | | | | | | | | | Move xilinx_dsp to before alumacc | Eddie Hung | 2019-08-08 | 1 | -6/+4 |
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| | * | | | | | | | | | Change $__softmul back to $mul | Eddie Hung | 2019-08-01 | 1 | -0/+1 |
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| | * | | | | | | | | | Use single DSP_SIGNEDONLY macro | Eddie Hung | 2019-07-18 | 1 | -1/+1 |
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| | * | | | | | | | | | Update comment | Eddie Hung | 2019-07-17 | 1 | -5/+3 |
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| | * | | | | | | | | | Revert drop down to 24x16 multipliers for all | Eddie Hung | 2019-07-16 | 1 | -1/+1 |
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| | * | | | | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-07-16 | 1 | -1/+5 |
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index : iCE40/yosys | |
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