| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | greenpak4: Inverted D latch cells now have nQ instead of Q as output port ↵ | Andrew Zonenberg | 2016-12-10 | 1 | -15/+15 | |
| | | | | | name for consistency | |||||
| * | Added GP_DLATCH and GP_DLATCHI | Andrew Zonenberg | 2016-12-05 | 1 | -0/+18 | |
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| * | Initial implementation of techlib support for GreenPAK latches. ↵ | Andrew Zonenberg | 2016-12-05 | 2 | -0/+120 | |
| | | | | | Instantiation only, no behavioral inference yet. | |||||
| * | Updated help text for synth_greenpak4 | Andrew Zonenberg | 2016-12-05 | 1 | -0/+2 | |
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| * | Indenting fixes in gowin sim cell lib | Clifford Wolf | 2016-11-08 | 1 | -20/+28 | |
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| * | Added hex constant support to write_verilog | Clifford Wolf | 2016-11-03 | 1 | -1/+1 | |
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| * | iCE40 flow is not experimental anymore | Clifford Wolf | 2016-11-01 | 1 | -1/+1 | |
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| * | Added initial version of "synth_gowin" | Clifford Wolf | 2016-11-01 | 4 | -0/+266 | |
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| * | Fixed typo in last commit | Andrew Zonenberg | 2016-10-18 | 1 | -1/+1 | |
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| * | greenpak4: Added GP_PGEN cell definition | Andrew Zonenberg | 2016-10-18 | 1 | -0/+21 | |
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| * | Added GLITCH_FILTER parameter to GP_DELAY | Andrew Zonenberg | 2016-10-18 | 1 | -3/+2 | |
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| * | greenpak4: added model for GP_EDGEDET block | Andrew Zonenberg | 2016-10-18 | 1 | -0/+10 | |
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| * | greenpak4: Changed parameters for GP_SYSRESET | Andrew Zonenberg | 2016-10-16 | 1 | -1/+2 | |
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| * | Added $anyseq cell type | Clifford Wolf | 2016-10-14 | 1 | -0/+12 | |
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| * | Added $global_clock verilog syntax support for creating $ff cells | Clifford Wolf | 2016-10-14 | 2 | -2/+23 | |
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| * | Added $ff and $_FF_ cell types | Clifford Wolf | 2016-10-12 | 2 | -1/+14 | |
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| * | Added "prep -nokeepdc" | Clifford Wolf | 2016-09-30 | 1 | -4/+12 | |
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| * | Added "prep -nomem" | Clifford Wolf | 2016-08-30 | 1 | -6/+16 | |
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| * | Removed $aconst cell type | Clifford Wolf | 2016-08-30 | 1 | -12/+0 | |
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| * | Removed $predict again | Clifford Wolf | 2016-08-28 | 1 | -8/+0 | |
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| * | Added "wreduce -memx" | Clifford Wolf | 2016-08-20 | 1 | -2/+6 | |
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| * | Added memory_memx pass, "memory -memx", and "prep -memx" | Clifford Wolf | 2016-08-19 | 1 | -2/+17 | |
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| * | Added greenpak4_dffinv | Clifford Wolf | 2016-08-15 | 3 | -0/+199 | |
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| * | greenpak4: Changed name of inverted output ports for consistency | Andrew Zonenberg | 2016-08-14 | 2 | -19/+19 | |
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| * | greenpak4: Added GP_DFFxI cells | Andrew Zonenberg | 2016-08-14 | 2 | -0/+68 | |
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| * | greenpak4: Renamed ports for better consistency (see azonenberg/openfpga:#6) | Andrew Zonenberg | 2016-08-13 | 1 | -10/+10 | |
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| * | synth_greenpak4: use attrmvcp to move LOC from wires to cells. | whitequark | 2016-08-10 | 1 | -0/+2 | |
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| * | Added $anyconst and $aconst | Clifford Wolf | 2016-07-27 | 1 | -0/+24 | |
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| * | Added $initstate cell type and vlog function | Clifford Wolf | 2016-07-21 | 1 | -0/+17 | |
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| * | After reading the SV spec, using non-standard predict() instead of expect() | Clifford Wolf | 2016-07-21 | 1 | -9/+1 | |
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| * | Added basic support for $expect cells | Clifford Wolf | 2016-07-13 | 1 | -0/+16 | |
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| * | Added GP_DAC cell | Andrew Zonenberg | 2016-07-11 | 1 | -0/+8 | |
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| * | Removed VOUT port of GP_BANDGAP | Andrew Zonenberg | 2016-07-11 | 1 | -1/+1 | |
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| * | Removed splitnets in prep for new gp4par parser | Andrew Zonenberg | 2016-07-11 | 1 | -1/+0 | |
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| * | Added "prep -auto-top" and "synth -auto-top" | Clifford Wolf | 2016-07-11 | 2 | -6/+23 | |
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| * | greenpak4: add GP_COUNT{8,14}_ADV cells. | whitequark | 2016-07-10 | 1 | -0/+26 | |
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| * | Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations | Clifford Wolf | 2016-07-08 | 2 | -13/+24 | |
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| * | Improved ice40_ffinit error reporting | Clifford Wolf | 2016-06-30 | 1 | -1/+5 | |
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| * | Added "deminout" | Clifford Wolf | 2016-06-19 | 1 | -0/+1 | |
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| * | Improved support for $sop cells | Clifford Wolf | 2016-06-17 | 2 | -4/+4 | |
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| * | Added $sop cell type and "abc -sop" | Clifford Wolf | 2016-06-17 | 1 | -0/+28 | |
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| * | Added "nlutmap -assert" | Clifford Wolf | 2016-06-09 | 1 | -3/+3 | |
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| * | Do not run "wreduce" in "prep -ifx" | Clifford Wolf | 2016-06-08 | 1 | -2/+3 | |
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| * | Added "proc_mux -ifx" | Clifford Wolf | 2016-06-06 | 1 | -2/+11 | |
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| * | Added GP_DELAY cell | Andrew Zonenberg | 2016-05-07 | 1 | -0/+29 | |
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| * | Fixed typo in port name | Andrew Zonenberg | 2016-05-07 | 1 | -1/+1 | |
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| * | Fixed extra semicolon | Andrew Zonenberg | 2016-05-07 | 1 | -1/+1 | |
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| * | Fixed typo in parameter name | Andrew Zonenberg | 2016-05-07 | 1 | -1/+1 | |
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| * | Added simulation timescale declaration | Andrew Zonenberg | 2016-05-07 | 1 | -0/+2 | |
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| * | Added synth_ice40 support for latches via logic loops | Clifford Wolf | 2016-05-06 | 3 | -0/+13 | |
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