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* Add first draft of eASIC back-endClifford Wolf2017-09-292-0/+191
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* Fix synth_ice40 doc regarding -top defaultClifford Wolf2017-09-291-1/+1
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* Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted.Andrew Zonenberg2017-09-142-2/+4
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* Initial support for extraction of counters with clock enableAndrew Zonenberg2017-09-141-21/+65
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* Merge pull request #406 from azonenberg/coolrunner-techmapClifford Wolf2017-09-022-18/+125
|\ | | | | Coolrunner techmapping improvements
| * coolrunner2: Finish fixing special-use p-termsRobert Ou2017-09-011-8/+20
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| * coolrunner2: Generate a feed-through AND term when necessaryRobert Ou2017-09-011-13/+31
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| * coolrunner2: Initial fixes for special p-termsRobert Ou2017-09-012-1/+81
| | | | | | | | | | Certain signals can only be controlled by a product term and not a sum-of-products. Do the initial work for fixing this.
| * coolrunner2: Fix mapping of flip-flopsRobert Ou2017-09-011-1/+0
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| * coolrunner2: Combine some for loops togetherRobert Ou2017-09-011-16/+14
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* | Fixed typo in error messageAndrew Zonenberg2017-09-011-1/+1
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* | Added blackbox $__COUNT_ cell modelAndrew Zonenberg2017-09-012-0/+18
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* | Refactoring: moved modules still in cells_sim to cells_sim_wipAndrew Zonenberg2017-09-013-136/+138
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* Merge branch 'master' of https://github.com/cliffordwolf/yosys into ↵Andrew Zonenberg2017-08-301-34/+34
|\ | | | | | | counter-extraction
| * Reformatted GP_COUNTx_ADV resets to avoid Yosys thinking that they're ↵Andrew Zonenberg2017-08-281-34/+34
| | | | | | | | multi-edge-sensitive and getting confused.
* | extract_counter: Minor changes requested to comply with upstream policy, ↵Andrew Zonenberg2017-08-302-4/+4
| | | | | | | | fixed a few typos
* | Finished refactoring counter extraction to be nice and generic. Implemented ↵Andrew Zonenberg2017-08-282-1/+69
| | | | | | | | techmapping from $__COUNT_ to GP_COUNTx cells.
* | Refactoring: Renamed greenpak4_counters pass to extract_counter, moved it to ↵Andrew Zonenberg2017-08-283-515/+1
|/ | | | techmap/ since it's going to become a generic pass
* Fixed bug causing GP_SPI model to not synthesizeAndrew Zonenberg2017-08-271-2/+2
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* Fixed more issues with GreenPAK counter sim modelsAndrew Zonenberg2017-08-151-19/+23
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* Updated PGEN model to have level triggered reset (matches actual hardware ↵Andrew Zonenberg2017-08-151-4/+4
| | | | behavior
* Fixed bug in GP_COUNTx modelAndrew Zonenberg2017-08-151-7/+12
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* Fixed bug where GP_COUNTx_ADV would wrap even when KEEP was highAndrew Zonenberg2017-08-151-47/+47
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* Merge pull request #381 from azonenberg/countfixClifford Wolf2017-08-144-504/+900
|\ | | | | Added better behavioral models for GreenPAK counters. Refactored cells_sim into two files so analog/mixed signal stuff is separate
| * Fixed typo in GP_COUNT8 sim modelAndrew Zonenberg2017-08-141-1/+1
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| * Fixed typo in error messageAndrew Zonenberg2017-08-141-1/+1
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| * Changed LEVEL resets for GP_COUNTx to be properly synthesizeableAndrew Zonenberg2017-08-141-48/+60
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| * Changed LEVEL resets to be edge triggered anywayAndrew Zonenberg2017-08-141-4/+4
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| * Added level-triggered reset support to GP_COUNTx simulation modelsAndrew Zonenberg2017-08-141-2/+68
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| * Fixed undeclared "count" in GP_COUNT8_ADVAndrew Zonenberg2017-08-141-0/+2
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| * Fixed undeclared "count" in GP_COUNT14_ADVAndrew Zonenberg2017-08-141-0/+2
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| * Fixed typo in last commitAndrew Zonenberg2017-08-141-3/+3
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| * Finished initial GP_COUNT8/14/8_ADV/14_ADV sim models. Don't support clock ↵Andrew Zonenberg2017-08-142-37/+293
| | | | | | | | divide, but do everything else.
| * Fixed typo in COUNT8 modelAndrew Zonenberg2017-08-141-2/+2
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| * Moved GP_POR out of digital cells b/c it has delaysAndrew Zonenberg2017-08-142-21/+21
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| * Improved cells_sim_digital model for GP_COUNT8Andrew Zonenberg2017-08-142-40/+75
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| * Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digitalAndrew Zonenberg2017-08-144-428/+451
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* | coolrunner2: Add INVERT parameter to some BUFGsRobert Ou2017-08-141-2/+6
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* | coolrunner2: Add FFs with clock enable to cells_sim.vRobert Ou2017-08-141-0/+60
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* Add techlibs/xilinx/lut2lut.vClifford Wolf2017-07-102-0/+66
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* Fix some c++ clang compiler errorsClifford Wolf2017-07-031-3/+3
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* Apply minor coding style changes to coolrunner2 targetClifford Wolf2017-07-032-1/+1
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* Merge pull request #352 from rqou/masterClifford Wolf2017-07-036-0/+645
|\ | | | | Initial Coolrunner-II support
| * coolrunner2: Add a few more primitivesRobert Ou2017-06-251-0/+110
| | | | | | | | These cannot be inferred yet, but add them to cells_sim.v for now
| * coolrunner2: Initial mapping of latchesRobert Ou2017-06-254-0/+63
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| * coolrunner2: Initial mapping of DFFsRobert Ou2017-06-254-0/+76
| | | | | | | | | | All DFFs map to either FDCP (matches Xilinx) or a custom FDCP_N (negative-edge triggered)
| * coolrunner2: Remove redundant INVERT_PTCRobert Ou2017-06-252-4/+1
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| * coolrunner2: Remove debug printsRobert Ou2017-06-251-2/+0
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| * coolrunner2: Correctly handle $_NOT_ after $sopRobert Ou2017-06-251-5/+41
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| * coolrunner2: Also construct the XOR cell in the macrocellRobert Ou2017-06-252-7/+34
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