aboutsummaryrefslogtreecommitdiffstats
path: root/chipset_enable.c
Commit message (Expand)AuthorAgeFilesLines
* ichspi: Add Intel Alder Lake-S supportMichał Kopeć2022-05-191-0/+9
* ichspi: Add Jasper Lake supportEdward O'Callaghan2022-04-141-0/+9
* hwaccess_x86_msr: rename msr function to msr_xxxThomas Heijligen2022-04-131-6/+6
* ichspi: Add support for Meteor LakeSubrata Banik2022-03-301-0/+9
* pcidev: Move pci_dev_find() from internal to canonical placeEdward O'Callaghan2022-03-221-3/+3
* ichspi: Add Alder Lake supportEdward O'Callaghan2022-03-071-0/+10
* pcidev: Move scandev_inclass logic from internal to pcidevEdward O'Callaghan2022-03-041-3/+3
* Add Elkhart Lake supportWerner Zeh2022-02-041-0/+9
* hwaccess: fix build on non-x86 targetsPeter Marheine2022-01-251-2/+3
* hwaccess: move mmio functions into hwaccess_physmapThomas Heijligen2022-01-201-1/+0
* chipset_enable.c: Add TGP-H IDsTim Crawford2022-01-051-0/+9
* physmap: rename to hwaccess_physmap, create own headerThomas Heijligen2021-12-221-0/+1
* hwaccess physmap: move x86 msr related code into own filesThomas Heijligen2021-12-221-0/+1
* hwaccess: move x86 port I/O related code into own filesThomas Heijligen2021-12-221-0/+1
* pci.h: move include into own wrapperThomas Heijligen2021-12-221-0/+1
* chipset_enable.c: Mark Intel Z390 as DEPmelvyn22021-11-171-1/+1
* Add Tiger Lake U Premium supportMichał Żygowski2021-11-171-0/+14
* chipset_enable.c: Mark Z97 as DEPSophie van Soest2021-09-131-1/+1
* Add support for Intel Emmitsburg PCHJonathan Zhang2021-09-011-0/+1
* chipset_enable.c: Add Gemini Lake eSPI PCI device IDAngel Pons2021-05-181-0/+1
* Add Gemini Lake supportAngel Pons2021-05-161-0/+9
* chipset_enable.c: Add IDs for H310C and B365 PCHsAngel Pons2021-04-271-0/+2
* chipset_enable.c: Add CMP-H IDsGaggery Tsai2021-04-261-0/+7
* chipset_enable: Mark QS67 as DEPEvgeny Zinoviev2021-04-241-1/+1
* chipset_enable.c: Add PCI ID for Comet Lake U BaseSam McNally2021-03-111-0/+1
* chipset_enable: Mark Intel C216 as DEPJacob Garber2021-02-281-1/+1
* chipset_enable.c: Mark Intel H110 as DEPAngel Pons2020-12-181-1/+1
* chipset_enable.c: mark "Broadwell U Base" as DEPNikolai Artemiev2020-12-141-1/+1
* chipset_enable.c: Validate physmap() return rcrb valueEdward O'Callaghan2020-12-021-0/+2
* chipset_enable.c: Mark Intel Q67 as DEPAngel Pons2020-11-231-1/+1
* chipset_enable.c: Add Intel pch7 did=0x1e4{1,2,3} supportEdward O'Callaghan2020-11-141-0/+3
* chipset_enable.c: check return value from rphysmap() callEdward O'Callaghan2020-10-271-0/+2
* Add support for Comet Lake-U/400-series PCHMatt DeVillier2020-09-241-0/+9
* chipset_enable: Mark Intel Q77 as DEPJacob Garber2020-08-291-1/+1
* add PCI IDs for additional c620 series PCH chipsJonathan Zhang2020-08-271-0/+3
* chipset_enable.c: Add support for Intel C620 Series Chipset SPI ControllerLuka Kovacic2020-08-251-0/+1
* chipset_enable: add PCI ID for APL-I (Broxton)Jan Samek2020-07-101-0/+1
* chipset_enable.c: Spell `BIOS` in uppercaseAngel Pons2020-05-031-1/+1
* chipset_enable.c: Disable SPI on ICH7 if booted from LPCAngel Pons2020-04-171-0/+8
* chipset_enable.c: Add more Lewisburg PCH IDsAngel Pons2020-03-271-0/+8
* chipset_enable: Mark Intel HM75 as DEPEvgeny Zinoviev2020-03-191-1/+1
* chipset_enable.c: Mark Skylake U Premium as DEPAngel Pons2020-03-191-1/+1
* chipset_enable.c: Add Ice Lake U to known and tested systemsJohanna Schander2020-02-091-0/+1
* chipset_enable: Add Kaby Lake U Prem. to known and tested systemsWim Vervoorn2020-01-221-1/+1
* chipset_enable.c: Mark Intel HM76 as DEPAngel Pons2019-12-211-1/+1
* chipset_enable.c: Mark Intel Q75 as DEPAngel Pons2019-10-081-1/+1
* chipset_enable: Mark Intel CM236 and CM246 as DEPNico Huber2019-08-081-2/+2
* chipset_enable: Add support for Cannon Lake U PremiumMatt DeVillier2019-08-081-0/+1
* ichspi: Add support for discrete Cannon Lake PCHsNico Huber2019-08-081-10/+10
* chipset_enable: Add support for discrete Cannon Lake PCHsThomas Heijligen2019-08-081-0/+18
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 02:05:07 +0000