Add testcase for #65

1 files changed, 20 insertions, 0 deletions

diff --git a/testsuite/issues/issue65/latch3.vhdl b/testsuite/issues/issue65/latch3.vhdl
new file mode 100644
index 0000000..e4518fe
--- /dev/null
+++ b/testsuite/issues/issue65/latch3.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity latch is
+  port (
+    signal clk          : in std_logic;
+    signal data         : in std_logic
+    );
+end entity;
+
+
+
+architecture rtl of latch is
+  signal other         : std_logic := '0';        
+begin
+  
+  default clock is rising_edge(clk);
+  assert always {true}
+    |=> next (data = other);  
+end architecture;