Sign extend 32b literals (#61)

* sign extend 32b literals

* Fix undefined behavior

Right shift of a signed values is undefined but does
arithemetic shift in practice.
However, shifting by more than one int width
is also undefined but *wraps around*.

This caused bit/log to work because it'd shift mod 32.
But it actually cause the UL32 to be wrong
because it'd just repeat the value rather than extending.

* zero pad unsigned and add signed

* add testsuite

2 files changed, 27 insertions, 0 deletions

diff --git a/testsuite/pr61/testsuite.sh b/testsuite/pr61/testsuite.sh
new file mode 100755
index 0000000..3ff1a15
--- /dev/null
+++ b/testsuite/pr61/testsuite.sh
@@ -0,0 +1,12 @@
+#!/bin/sh
+
+. ../testenv.sh
+
+run_yosys -p "ghdl vector.vhdl -e vector; dump -o vector.il"
+
+grep -q 0000000000000000000000000000000011111111111111111111111111111010 vector.il || exit 1
+grep -q 0000000011111111111111111111111111111111111111111111111100000000 vector.il || exit 1
+grep -q 1111111111111111111111111111111111111111111111111111111111111111 vector.il || exit 1
+grep -q 0000111111111111111111111111111111111111111111111111111111110000 vector.il || exit 1
+
+clean
diff --git a/testsuite/pr61/vector.vhdl b/testsuite/pr61/vector.vhdl
new file mode 100644
index 0000000..61a0d67
--- /dev/null
+++ b/testsuite/pr61/vector.vhdl
@@ -0,0 +1,15 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity vector is
+  port (v: out signed(63 downto 0);
+        u: out unsigned(63 downto 0));
+end vector;
+
+architecture synth of vector is
+
+begin
+  v <= signed'(x"0ffffffffffffff0")+(-1);
+  u <= unsigned'(x"00ffffffffffff00")+4294967290;
+end synth;