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* fixed VLO/VHI primitves (#185)HEADmasterrobin2023-04-191-9/+9
* testsuite: add a test for #2392Tristan Gingold2023-03-1510-0/+548
* testsuite: add a test for #2392Tristan Gingold2023-03-155-0/+141
* gha: bump to actions@v3Tristan Gingold2023-03-091-1/+1
* testsuite: add a test, close ghdl/ghdl#2373Tristan Gingold2023-03-096-0/+230
* ci: sby now depends on click (hdl/containers#63)Unai Martinez-Corral2022-12-171-1/+3
* readme: update shield syntax (badges/shields#8671)Unai Martinez-Corral2022-12-171-1/+1
* testsuite: adjust previous commit to latest yosys. For #171Tristan Gingold2022-09-011-1/+1
* testsuite: add a test for #171Tristan Gingold2022-08-312-0/+126
* Fix to block RAM handling as per https://github.com/YosysHQ/yosys/issues/3364...Alastair M. Robinson2022-08-311-1/+1
* ghdl.cc: handle dlatchTristan Gingold2022-07-141-0/+4
* Makefile: patches regarding DESTDIR and plugin install dir (#166)Unai Martinez-Corral2022-01-111-2/+3
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| * Allow overriding plugin installation directoryDaniel Gröber2022-01-081-3/+3
| * Support installing into $DESTDIRDaniel Gröber2022-01-081-2/+3
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* Use mem v2 cellsTristan Gingold2021-11-271-93/+125
* Makefile: add dependenciesTristan Gingold2021-11-271-0/+2
* ghdl.cc: adjust after renaming of instances attributesTristan Gingold2021-11-171-7/+7
* ghdl.cc: propagate ports attributesTristan Gingold2021-11-171-8/+16
* testsuite: add a test for #160Tristan Gingold2021-10-113-0/+64
* ghdl.cc: strip signals on memory init data. Fix #160Tristan Gingold2021-10-111-2/+9
* testsuite: add tests for #159Tristan Gingold2021-10-093-0/+43
* testsuite/issue: add a test for #154Tristan Gingold2021-10-032-0/+67
* ghdl.cc: set attributes on signals when they are created. Fix #154Tristan Gingold2021-10-031-40/+22
* ghdl.cc: display compile date and git hashTristan Gingold2021-10-032-1/+8
* testsuite: add a first test to display config and versionTristan Gingold2021-10-031-0/+8
* readme: remove TOC (now supported in the GitHub UI)umarcor2021-10-031-8/+0
* ci: clean commentumarcor2021-10-031-1/+1
* ci: add do_ghdlumarcor2021-10-031-15/+33
* ci/synth: use yosys container from hdl/containersumarcor2021-10-031-7/+27
* ci/formal: use pkg containers from hdl/containersumarcor2021-10-031-3/+11
* testsuite: add a test for #158Tristan Gingold2021-10-025-0/+160
* ghdl.cc: always create a wire for signal/isignal. Fix #158Tristan Gingold2021-10-021-7/+3
* Added proper components.vhdl with uppercase symbolsMartin2021-09-151-4243/+4243
* testsuite: add a test for ghdl/ghdl#1699Tristan Gingold2021-03-272-0/+50
* ghdl.cc: remove unused/extra memory module. Fix #1699Tristan Gingold2021-03-271-10/+0
* testsuite/formal: add a test for #145Tristan Gingold2021-03-243-0/+64
* ghdl.cc: handle read after write for memories. Fix #145Tristan Gingold2021-03-241-1/+9
* testsuite: add a test for ghdl/ghdl#1682Tristan Gingold2021-03-172-0/+48
* ghdl.cc: handle attributes on output portsTristan Gingold2021-03-171-8/+12
* Makefile: use CFLAGS/LDFLAGS from environmentXiretza2021-03-131-2/+1
* ghdl.cc: adjust include pathTristan Gingold2021-03-071-1/+1
* testsuite: add testcase for ghdl/ghdl#1610Tristan Gingold2021-01-252-0/+42
* ghdl.cc: handle gclk attributes on dff. For ghdl/ghdl#1610Tristan Gingold2021-01-251-13/+70
* Minor rework on attributes.Tristan Gingold2021-01-251-5/+19
* readme: in Yosys's makefile GHDL_DIR was renamed to GHDL_PREFIX (YosysHQ/yosy...eine2021-01-011-1/+1
* readme: update guidelines, update container image names, add ref to mingw-w64...eine2020-12-291-34/+48
* remove yosys.diff, was upstreamed to YosysHQ/yosyseine2020-12-291-27/+0
* Fix mult18x18d component to match yosys verilogJulianKemmerer2020-12-191-260/+260
* ci: update deps from ghdl/* to hdlc/*eine2020-11-191-2/+11
* example/blackbox: tune the test for previous commitTristan Gingold2020-11-182-2/+3
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