| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | testsuite: add a test for #160 | Tristan Gingold | 2021-10-11 | 3 | -0/+64 |
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| * | ghdl.cc: strip signals on memory init data. Fix #160 | Tristan Gingold | 2021-10-11 | 1 | -2/+9 |
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| * | testsuite: add tests for #159 | Tristan Gingold | 2021-10-09 | 3 | -0/+43 |
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| * | testsuite/issue: add a test for #154 | Tristan Gingold | 2021-10-03 | 2 | -0/+67 |
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| * | ghdl.cc: set attributes on signals when they are created. Fix #154 | Tristan Gingold | 2021-10-03 | 1 | -40/+22 |
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| * | ghdl.cc: display compile date and git hash | Tristan Gingold | 2021-10-03 | 2 | -1/+8 |
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| * | testsuite: add a first test to display config and version | Tristan Gingold | 2021-10-03 | 1 | -0/+8 |
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| * | readme: remove TOC (now supported in the GitHub UI) | umarcor | 2021-10-03 | 1 | -8/+0 |
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| * | ci: clean comment | umarcor | 2021-10-03 | 1 | -1/+1 |
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| * | ci: add do_ghdl | umarcor | 2021-10-03 | 1 | -15/+33 |
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| * | ci/synth: use yosys container from hdl/containers | umarcor | 2021-10-03 | 1 | -7/+27 |
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| * | ci/formal: use pkg containers from hdl/containers | umarcor | 2021-10-03 | 1 | -3/+11 |
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| * | testsuite: add a test for #158 | Tristan Gingold | 2021-10-02 | 5 | -0/+160 |
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| * | ghdl.cc: always create a wire for signal/isignal. Fix #158 | Tristan Gingold | 2021-10-02 | 1 | -7/+3 |
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| * | Added proper components.vhdl with uppercase symbols | Martin | 2021-09-15 | 1 | -4243/+4243 |
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| * | testsuite: add a test for ghdl/ghdl#1699 | Tristan Gingold | 2021-03-27 | 2 | -0/+50 |
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| * | ghdl.cc: remove unused/extra memory module. Fix #1699 | Tristan Gingold | 2021-03-27 | 1 | -10/+0 |
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| * | testsuite/formal: add a test for #145 | Tristan Gingold | 2021-03-24 | 3 | -0/+64 |
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| * | ghdl.cc: handle read after write for memories. Fix #145 | Tristan Gingold | 2021-03-24 | 1 | -1/+9 |
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| * | testsuite: add a test for ghdl/ghdl#1682 | Tristan Gingold | 2021-03-17 | 2 | -0/+48 |
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| * | ghdl.cc: handle attributes on output ports | Tristan Gingold | 2021-03-17 | 1 | -8/+12 |
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| * | Makefile: use CFLAGS/LDFLAGS from environment | Xiretza | 2021-03-13 | 1 | -2/+1 |
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| * | ghdl.cc: adjust include path | Tristan Gingold | 2021-03-07 | 1 | -1/+1 |
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| * | testsuite: add testcase for ghdl/ghdl#1610 | Tristan Gingold | 2021-01-25 | 2 | -0/+42 |
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| * | ghdl.cc: handle gclk attributes on dff. For ghdl/ghdl#1610 | Tristan Gingold | 2021-01-25 | 1 | -13/+70 |
| | | | | | Also attribute nets. | ||||
| * | Minor rework on attributes. | Tristan Gingold | 2021-01-25 | 1 | -5/+19 |
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| * | readme: in Yosys's makefile GHDL_DIR was renamed to GHDL_PREFIX ↵ | eine | 2021-01-01 | 1 | -1/+1 |
| | | | | | (YosysHQ/yosys#2515) | ||||
| * | readme: update guidelines, update container image names, add ref to ↵ | eine | 2020-12-29 | 1 | -34/+48 |
| | | | | | mingw-w64-*-eda package groups | ||||
| * | remove yosys.diff, was upstreamed to YosysHQ/yosys | eine | 2020-12-29 | 1 | -27/+0 |
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| * | Fix mult18x18d component to match yosys verilog | JulianKemmerer | 2020-12-19 | 1 | -260/+260 |
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| * | ci: update deps from ghdl/* to hdlc/* | eine | 2020-11-19 | 1 | -2/+11 |
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| * | example/blackbox: tune the test for previous commit | Tristan Gingold | 2020-11-18 | 2 | -2/+3 |
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| * | Use ':' instead of '$' for number names | Tristan Gingold | 2020-11-18 | 1 | -2/+3 |
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| * | ghdl.cc: allow extended identifier of length 1 | Tristan Gingold | 2020-11-18 | 1 | -1/+1 |
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| * | Add a test for previous commit | Tristan Gingold | 2020-11-18 | 4 | -0/+70 |
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| * | Try to convert extended name to a name | Tristan Gingold | 2020-11-18 | 1 | -1/+31 |
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| * | ci: disable trigger | eine | 2020-11-12 | 1 | -9/+12 |
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| * | ci: add command-line arguments | Rodrigo Alejandro Melo | 2020-10-03 | 2 | -1/+33 |
| | | | | | - add *.edif and *.ilang files to .gitignore | ||||
| * | '%' is not supported by Xilinx ISE edif2ngc. Fix #134 | eine | 2020-10-02 | 1 | -1/+2 |
| | | | | | Authored-By: Tristan Gingold <tgingold@free.fr> | ||||
| * | testsuite/issues: renames pr61 to issue61 | Tristan Gingold | 2020-09-27 | 2 | -0/+0 |
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| * | testsuite/issues: adjust pr61 | Tristan Gingold | 2020-09-27 | 1 | -1/+2 |
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| * | testsuite: add a test for ghdl/ghdl#1421 | Tristan Gingold | 2020-09-27 | 3 | -0/+133 |
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| * | readme: update shields/badges | eine | 2020-08-31 | 1 | -2/+2 |
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| * | ci: fix synth_formal.dockerfile URL | eine | 2020-07-24 | 1 | -1/+1 |
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| * | ci: dispatch after push to 'master' only | eine | 2020-06-05 | 1 | -0/+1 |
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| * | ci: trigger repository_dispatch in ghdl/docker | eine | 2020-06-05 | 1 | -0/+7 |
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| * | Add formal tests for mod/rem | Xiretza | 2020-05-30 | 3 | -1/+113 |
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| * | Fix signed modulo behaviour | Xiretza | 2020-05-30 | 1 | -4/+5 |
| | | | | | | | | | | Yosys' $mod cell is the modulo of truncating division, known as "rem" in VHDL. The new $modfloor cell is the modulo of flooring division, known as "mod" in VHDL. "mod" now synthesizes correctly for negative numbers. | ||||
| * | Fix testsuite failing on second run | Xiretza | 2020-05-30 | 1 | -1/+1 |
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| * | Add reduce_xor support to the Yosys plugin | rlee287 | 2020-05-28 | 1 | -0/+4 |
| | | | | | This is a followup for ghdl/ghdl issue 1342 | ||||
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index : iCE40/ghdl-yosys-plugin | |
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