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| author | Tristan Gingold <tgingold@free.fr> | 2016-06-30 06:15:03 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2016-07-03 14:16:16 +0200 |
| commit | 906d23d23591b2040b3554e7aa39ecfe0c9a1e1b (patch) | |
| tree | e3730d31d53b8d659cea4266399583fde7af6c2c /testsuite/gna | |
| parent | 787d1d010ba53f2572aa11a78407e846ee4061dc (diff) | |
| download | ghdl-906d23d23591b2040b3554e7aa39ecfe0c9a1e1b.tar.gz ghdl-906d23d23591b2040b3554e7aa39ecfe0c9a1e1b.tar.bz2 ghdl-906d23d23591b2040b3554e7aa39ecfe0c9a1e1b.zip | |
Add more tests for issue #2.
Diffstat (limited to 'testsuite/gna')
| -rw-r--r-- | testsuite/gna/issue2/repro.vhdl | 15 | ||||
| -rw-r--r-- | testsuite/gna/issue2/repro2.vhdl | 15 | ||||
| -rwxr-xr-x | testsuite/gna/issue2/testsuite.sh | 14 |
3 files changed, 38 insertions, 6 deletions
diff --git a/testsuite/gna/issue2/repro.vhdl b/testsuite/gna/issue2/repro.vhdl new file mode 100644 index 000000000..e58e894bf --- /dev/null +++ b/testsuite/gna/issue2/repro.vhdl @@ -0,0 +1,15 @@ +entity repro is + port ( + foo: in boolean + ); +end entity; + +architecture foo of repro is + signal foo_int: boolean; +begin +FUMBLE: + entity work.repro + port map ( + foo => foo_int + ); +end architecture; diff --git a/testsuite/gna/issue2/repro2.vhdl b/testsuite/gna/issue2/repro2.vhdl new file mode 100644 index 000000000..ae989a7a9 --- /dev/null +++ b/testsuite/gna/issue2/repro2.vhdl @@ -0,0 +1,15 @@ +entity repro2 is + generic (depth : natural := 7); + port (foo: in boolean); +end entity; + +architecture foo of repro2 is + signal foo_int: boolean; +begin + cond: if depth > 0 generate + FUMBLE: + entity work.repro2 + generic map (depth => depth - 1) + port map (foo => foo_int); + end generate; +end architecture; diff --git a/testsuite/gna/issue2/testsuite.sh b/testsuite/gna/issue2/testsuite.sh index ffa23903f..bad36b3e9 100755 --- a/testsuite/gna/issue2/testsuite.sh +++ b/testsuite/gna/issue2/testsuite.sh @@ -5,16 +5,18 @@ GHDL_STD_FLAGS=--std=08 GHDL_FLAGS=--work=test +analyze repro.vhdl +analyze repro2.vhdl +elab_simulate repro2 + analyze sortnet_OddEvenSort.vhdl analyze sortnet_OddEvenSort_tb.vhdl elab_simulate --syn-binding sortnet_OddEvenSort_tb -if false; then - # Direct instantiation, not yet supported. - analyze sortnet_BitonicSort.vhdl - analyze sortnet_BitonicSort_tb.vhdl - elab_simulate sortnet_BitonicSort_tb -fi +# Direct instantiation, not yet supported. +analyze sortnet_BitonicSort.vhdl +analyze sortnet_BitonicSort_tb.vhdl +elab_simulate sortnet_BitonicSort_tb clean test |