testsuite/vets/vhdl-ams: fix syntax.

11 files changed, 17 insertions, 17 deletions

diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_cmos_inv_ramp.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_cmos_inv_ramp.ams
index 5aeb07ba0..7ab084991 100644
--- a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_cmos_inv_ramp.ams
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_cmos_inv_ramp.ams
@@ -40,7 +40,7 @@
 
 
 PACKAGE electricalSystem IS
-    NATURE electrical IS real ACROSS real THROUGH;
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
     FUNCTION POW(X,Y: real) RETURN real;
     FUNCTION SIN(X : real) RETURN real;
     FUNCTION EXP(X : real) RETURN real;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test123.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test123.ams
index 9d3e53e7b..9f94606c9 100644
--- a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test123.ams
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test123.ams
@@ -49,7 +49,7 @@
 -- +g and -g.
 ----------------------------------------------------------------------
 PACKAGE electricalSystem IS
-    NATURE electrical IS real ACROSS real THROUGH;
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
     FUNCTION SIN(X : real) RETURN real;
 --    alias ground is electrical'reference;
 END PACKAGE electricalSystem;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test134.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test134.ams
index 0f80d28c0..24e568282 100644
--- a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test134.ams
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test134.ams
@@ -54,7 +54,7 @@
 ---------------------------------------------------------------------------------
 PACKAGE electricalSystem IS
     SUBTYPE voltage is real;
-    NATURE electrical IS real ACROSS real THROUGH;
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
     FUNCTION SIN(X : real) RETURN real;
     FUNCTION EXP(X : real) RETURN real;
     FUNCTION SQRT(X : real) RETURN real;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test180.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test180.ams
index 3e33069e4..7a0e136b8 100644
--- a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test180.ams
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test180.ams
@@ -49,7 +49,7 @@
 -- codition.
 
 PACKAGE electricalSystem IS
-    NATURE electrical IS real ACROSS real THROUGH; -- GROUND REFERENCE;
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
     FUNCTION SIN(X : real) RETURN real;
     FUNCTION EXP(X : real) RETURN real;
 END PACKAGE electricalSystem;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test181.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test181.ams
index 4c7caf467..f8840367f 100644
--- a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test181.ams
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test181.ams
@@ -49,7 +49,7 @@
 -- codition.
 
 PACKAGE electricalSystem IS
-    NATURE electrical IS real ACROSS real THROUGH; -- GROUND REFERENCE;
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
     FUNCTION SIN(X : real) RETURN real;
     FUNCTION EXP(X : real) RETURN real;
 END PACKAGE electricalSystem;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/above_attr.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/above_attr.ams
index c3bf7abd0..1d3f0c689 100644
--- a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/above_attr.ams
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/above_attr.ams
@@ -65,7 +65,7 @@ ABSIG<=V1'above(V2+1.0);
             
  testbench:PROCESS
         VARIABLE outline : LINE;
-        VARIABLE Headline   : string(1 TO 33) :=
+        VARIABLE Headline   : string(1 TO 10) :=
             "time ABSIG";
         VARIABLE   seperator    : string(1 TO 1) := " ";
         VARIABLE   flag     : bit := '0';
@@ -77,7 +77,7 @@ ABSIG<=V1'above(V2+1.0);
             WRITE(outline,Headline);
             WRITELINE(outfile,outline);
         ELSE
-            WRITE(outline, now);
+            WRITE(outline, time'(now));
             WRITE(outline,seperator);
             IF (ABSIG = true) THEN
             tmp:='1';
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/generic_model.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/generic_model.ams
index eb636b540..e0427eb5c 100644
--- a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/generic_model.ams
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/generic_model.ams
@@ -112,7 +112,7 @@ BEGIN
 
  testbench:PROCESS
         VARIABLE outline : LINE;
-        VARIABLE Headline   : string(1 TO 8) :=
+        VARIABLE Headline   : string(1 TO 7) :=
             "time y ";
         VARIABLE   seperator    : string(1 TO 1) := " ";
         VARIABLE   flag     : bit := '0';
@@ -123,7 +123,7 @@ BEGIN
             WRITE(outline,Headline);
             WRITELINE(outfile,outline);
         ELSE
-            WRITE(outline, now);
+            WRITE(outline, time'(now));
             WRITE(outline,seperator);
             WRITE(outline,y);
             WRITE(outline,seperator);
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_1.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_1.ams
index 10fd3bbeb..c2be9b915 100644
--- a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_1.ams
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_1.ams
@@ -61,7 +61,7 @@ end process;
 
  testbench:PROCESS
         VARIABLE outline : LINE;
-        VARIABLE Headline   : string(1 TO 8) :=
+        VARIABLE Headline   : string(1 TO 6) :=
             "time y";
         VARIABLE   seperator    : string(1 TO 1) := " ";
         VARIABLE   flag     : bit := '0';
@@ -72,7 +72,7 @@ end process;
             WRITE(outline,Headline);
             WRITELINE(outfile,outline);
         ELSE
-            WRITE(outline, now);
+            WRITE(outline, time'(now));
             WRITE(outline,seperator);
             WRITE(outline,y);
             WRITE(outline,seperator);
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_2.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_2.ams
index dd80c233e..89b3a0100 100644
--- a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_2.ams
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_2.ams
@@ -111,7 +111,7 @@ BEGIN
 
  testbench:PROCESS
         VARIABLE outline : LINE;
-        VARIABLE Headline   : string(1 TO 8) :=
+        VARIABLE Headline   : string(1 TO 6) :=
             "time y";
         VARIABLE   seperator    : string(1 TO 1) := " ";
         VARIABLE   flag     : bit := '0';
@@ -122,7 +122,7 @@ BEGIN
             WRITE(outline,Headline);
             WRITELINE(outfile,outline);
         ELSE
-            WRITE(outline, now);
+            WRITE(outline, time'(now));
             WRITE(outline,seperator);
             WRITE(outline,y);
             WRITE(outline,seperator);
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/mixed_1.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/mixed_1.ams
index 37cd1280c..6cfd199a6 100644
--- a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/mixed_1.ams
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/mixed_1.ams
@@ -77,7 +77,7 @@ BEGIN
 
 testbench:PROCESS(y)
     VARIABLE outline : LINE;
-    VARIABLE Headline   : string(1 TO 52) :=
+    VARIABLE Headline   : string(1 TO 7) :=
       "time  y";
     VARIABLE   seperator    : string(1 TO 1) := " ";
     VARIABLE   flag     : bit := '0';
@@ -88,7 +88,7 @@ testbench:PROCESS(y)
       WRITE(outline,Headline);
       WRITELINE(outfile,outline);
     ELSE
-      WRITE(outline, now);
+      WRITE(outline, time'(now));
       WRITE(outline,seperator);  
       WRITE(outline, y);
       WRITE(outline, seperator);
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/mixed_2.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/mixed_2.ams
index c78005790..16bb65d58 100644
--- a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/mixed_2.ams
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/mixed_2.ams
@@ -76,7 +76,7 @@ BEGIN
 
 testbench:PROCESS(y,x)
     VARIABLE outline : LINE;
-    VARIABLE Headline   : string(1 TO 52) :=
+    VARIABLE Headline   : string(1 TO 9) :=
       "time  y x";
     VARIABLE   seperator    : string(1 TO 1) := " ";
     VARIABLE   flag     : bit := '0';
@@ -87,7 +87,7 @@ testbench:PROCESS(y,x)
       WRITE(outline,Headline);
       WRITELINE(outfile,outline);
     ELSE
-      WRITE(outline, now);
+      WRITE(outline, time'(now));
       WRITE(outline,seperator);  
       WRITE(outline, y);
       WRITE(outline, seperator);