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* synth-vhdl_expr: improve subtype conversionTristan Gingold2023-02-221-69/+160
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* testsuite/gna: add a test for #2353Tristan Gingold2023-02-196-0/+223
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* vhdl-sem_decls(sem_object_type_from_value): refine.Tristan Gingold2023-02-191-5/+20
| | | | | Only use object type when it completes an unconstrained array type like in vhdl 93.
* trans-chap2: elaborate dependencies of macro-expanded packages.Tristan Gingold2023-02-191-19/+38
| | | | Fix #2353
* testsuite/gna: add tests for #2350Tristan Gingold2023-02-138-0/+156
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* sem_record_aggregate: add a check for constraints. Fix #2350Tristan Gingold2023-02-131-11/+23
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* Make-lang.in: also generate Backend_VersionTristan Gingold2023-02-121-0/+2
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* doc: clarify diagnostic level output.Tristan Gingold2023-02-121-1/+5
| | | | Close #2351
* ghdl: print llvm or gcc backend version with --versionTristan Gingold2023-02-124-4/+15
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* testsuite/gna: add a test for #2349Tristan Gingold2023-02-114-0/+2703
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* ghdllocal, ghdlxml: adjust after previous commit; fix #2349Tristan Gingold2023-02-112-0/+6
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* vhdl-sem_lib: units during analysis can depend only on analyzed units.Tristan Gingold2023-02-111-0/+6
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* testsuite/synth: add a test for #2347Tristan Gingold2023-02-092-0/+49
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* synth-vhdl_eval: handle std_logic_arith.conv_std_logic_vectorTristan Gingold2023-02-093-0/+43
| | | | Fix #2347
* synth: preliminary work for PSL endpointsTristan Gingold2023-02-082-1/+19
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* simul: improve support of PSL endpointsTristan Gingold2023-02-082-10/+12
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* simul: improve handling of individual signal associationsTristan Gingold2023-02-081-3/+3
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* synth: do not handle null-vectors for to_hstring.Tristan Gingold2023-02-082-1/+18
| | | | For #2338
* testsuite/gna: add a test for #2346Tristan Gingold2023-02-086-0/+129
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* trans-chap8: fix a crash while checking bounds in signal assignments.Tristan Gingold2023-02-081-1/+1
| | | | Fix #2346
* trans-chap8: Fix individual assocs of signal parametersTristan Gingold2023-02-081-22/+44
| | | | (for non-suspendable procedures).
* simul: handle signal assignment to procedure individual associationsTristan Gingold2023-02-081-8/+19
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* trans-chap8: minor reindentationTristan Gingold2023-02-081-1/+1
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* synth: use same layout for records in memory as translateTristan Gingold2023-02-0810-70/+229
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* testsuite/gna: add a reproducer for #2344Tristan Gingold2023-02-082-0/+47
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* vhdl-canon: remove signal parameters for all-sensitized processes.Tristan Gingold2023-02-084-9/+54
| | | | Fix #2344
* synth: preliminary work to compute access bounds sizeTristan Gingold2023-02-053-2/+128
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* elab-vhdl_objtypes: rename acc_bnd_sz to acc_type_szTristan Gingold2023-02-053-7/+7
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* vhdl-prints: improve output of generate statementsTristan Gingold2023-02-041-12/+5
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* translate: add --no-elaboration flagTristan Gingold2023-02-045-2/+10
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* elab-vhdl_debug: handle package in subprogramsTristan Gingold2023-02-041-0/+13
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* simul: refactoring, expose more subprogramsTristan Gingold2023-02-043-35/+47
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* mcode/ortho_jit.adb: add option --be-gTristan Gingold2023-02-041-1/+1
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* testsuite/synth: rename testcase directory.Tristan Gingold2023-02-043-0/+0
| | | | For #2339
* testsuite/synth: add a test for #2336Tristan Gingold2023-02-033-0/+486
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* vhdl-sem_decls: fix a regression on subtype indication. Fix #2336Tristan Gingold2023-02-031-1/+1
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* vhdl: reduce use of is_anonymous_type_definitionTristan Gingold2023-02-036-34/+40
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* pyGHDL: reformatingTristan Gingold2023-02-032-3/+1
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* TBMTristan Gingold2023-02-024-12/+56
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* translate: improve support for Flag_ElaborationTristan Gingold2023-02-022-2/+10
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* testsuite/gna: add tests in bug056Tristan Gingold2023-02-024-0/+59
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* vhdl: avoid error storms in assertionsTristan Gingold2023-02-022-2/+4
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* trans-chap3: minor rewriteTristan Gingold2023-02-021-1/+1
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* testsuite/gna: add a test for #2337Tristan Gingold2023-02-023-0/+80
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* translate: rework translate_object_subtype_indication.Tristan Gingold2023-02-025-66/+83
| | | | Fix #2337
* testsuite/gna: add a test for #2336Tristan Gingold2023-01-316-0/+456
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* psl-build: fix fusion with epsilon. Fix #2336Tristan Gingold2023-01-311-0/+1
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* translate: add a flag to disable elaborationTristan Gingold2023-01-313-106/+125
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* elab-debugger: also pass top instance on break_timeTristan Gingold2023-01-313-4/+4
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* ghdlsimul: extract simul-main from simul-vhdl_simulTristan Gingold2023-01-316-110/+186
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