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* rework 'python', rename to 'pyGHDL'umarcor2020-12-2729-6478/+0
| | | | | | | | | | * Rename 'python' to 'pyGHDL'. * Let 'thin' be 'libghdl'. * Move move 'pyutils.py' from 'python/libghdl/vhdl' to a separate package ('pyGHDL/libghdl/utils/'). * Update 'vhdl_langserver' accordingly. * Rename 'vhdl_langserver' to 'lsp'. * Move 'ghdl-ls' to 'pyGHDL/cli'.
* libraries: Load_Std_Library: now return a status.Tristan Gingold2020-12-261-1/+6
| | | | | | Propagate this change to libghdl and python binding to avoid abort. For #1551
* py: run blackeine2020-12-162-723/+446
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* vhdl: handle locally static attributes on entity/architecture/configurationsTristan Gingold2020-12-082-1188/+1484
| | | | | | | | | | | | | Attributes of entity/architecture/configurations are expected to be locally static so that they can be referenced from outside (so on the non-instantiated entity). But many designs break this assumption. In relaxed mode, non-locally static attributes are allowed but now cannot be referenced outside the entity. Locally static attributes can be referenced from outside. Fix #1528
* py: run blackeine2020-09-262-723/+445
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* vhdl: parse subprogram instantiations. For #1470Tristan Gingold2020-09-242-1110/+1407
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* vhdl: recognize find_leftmost/find_rightmost. For #1460Tristan Gingold2020-09-161-182/+184
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* py: run blackeine2020-09-151-2/+1
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* vhdl: recognize reduce operations from numeric_std.Tristan Gingold2020-09-141-232/+269
| | | | Handle them in synthesis.
* py undefined symbolsumarcor2020-08-312-5/+5
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* ci: run black 20.8b1eine2020-08-271-2/+2
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* python: execute 'black'eine2020-08-2318-957/+727
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* py: adjust blank lines to PEP 8 for vhdl_langserver (#1434)m-kru2020-08-151-0/+2
| | | | | | Why? 1. Conform to PEP 8. 2. Easier to read. 3. Make tools, such as PyCharm, not complain.
* vhdl: recognize more operators for std_logic_unsigned/signed.Tristan Gingold2020-08-071-174/+200
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* vhdl: recognize more std_logic_arith operators.Tristan Gingold2020-08-072-300/+314
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* vhdl: parse and analyze force/release signal assignment statements.Tristan Gingold2020-08-012-273/+296
| | | | For #1416
* vhdl: add force and release tokens. For #1416Tristan Gingold2020-08-012-125/+127
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* vhdl: replace base_type with parent_type in nodesTristan Gingold2020-07-222-5/+5
| | | | | Only for subtype definition and remove base_type in type definitions. Allows to better track the addition of contraints.
* synth: handle std_logic_signed.conv_integer. For ghdl/ghdl-yosys-plugin#126Tristan Gingold2020-06-191-130/+131
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* vhdl: decode to_x01 (from ieee.std_logic_1164)Tristan Gingold2020-06-192-570/+591
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* vhdl: create default configuration for a vunit. Fix #1372Tristan Gingold2020-06-153-435/+444
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* vhdl: analyze and synth concurrent statements in vunit. Fix #1366Tristan Gingold2020-06-121-0/+5
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* Synthesis of PSL prev function.Tristan Gingold2020-06-022-5/+5
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* vhdl: parse PSL prev/stable/rose/fell builtin calls. For #662Tristan Gingold2020-06-023-117/+155
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* synth: handle reduction operators. Fix #1342Tristan Gingold2020-05-271-362/+366
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* vhdl-nodes: Rename and move shift/rotate predefined functions. Fix #1325Tristan Gingold2020-05-191-37/+37
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* synth: handle functional call to numeric_std binary operators. For #1313Tristan Gingold2020-05-161-81/+81
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* types: introduce Direction_Type, which replaces Iir_Direction.Tristan Gingold2020-04-202-14/+9
| | | | Global renaming.
* synth-oper: recognize more operations from std_logic_arith.Tristan Gingold2020-04-121-60/+84
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* vhdl: recognize math_real.floor. For #1210Tristan Gingold2020-04-112-339/+341
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* vhdl: handle pragma synthesis_on/synthesis_off.Tristan Gingold2020-04-111-180/+184
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* vhdl: recognize ext/sxt from std_logic_arith.Tristan Gingold2020-04-111-92/+94
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* vhdl: recognize comparaison of std_logic_arith.Tristan Gingold2020-04-111-12/+60
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* vhdl: add scalar_size. Size of scalar types is computed during analysis.Tristan Gingold2020-04-062-97/+108
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* vhdl: recognize reduce functions in std_logic_misc.Tristan Gingold2020-03-281-0/+12
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* synth: handle ieee.numeric_std.to_01Tristan Gingold2020-03-222-283/+288
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* vhdl: recognize minimum/maximum in numeric_std. For #1168Tristan Gingold2020-03-211-164/+176
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* synth: handle more operations from synsopsys packages.Tristan Gingold2020-03-141-77/+79
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* std_names: add *_reduce names.Tristan Gingold2020-03-131-183/+189
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* vhdl: recognize more std_logic_arith operations.Tristan Gingold2020-03-131-0/+32
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* vhdl-ieee-std_logic_arith: recognize more conversions.Tristan Gingold2020-03-112-183/+188
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* vhdl: recognize mod/rem operators.Tristan Gingold2020-03-101-162/+174
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* synthesis: add option --vendor-library= for synthesis.Tristan Gingold2020-03-103-169/+179
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* [PATCH] Add names for synopsys packages.Tristan Gingold2020-03-032-224/+228
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* Set version to 1.0-devTristan Gingold2020-02-281-1/+1
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* Release 0.37Tristan Gingold2020-02-281-1/+1
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* vhdl: recognize conversion functions from std_logic_1164Tristan Gingold2020-02-182-405/+415
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* synth: handle some rotation and shifts. Fix #1077Tristan Gingold2020-01-301-205/+209
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* synth: handle matching comparisons. Fix #1109Tristan Gingold2020-01-241-90/+126
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* synth: add id_abs gate. For #1101Tristan Gingold2020-01-201-71/+72
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