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path: root/src/synth/ghdlsynth_gates.h
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* synth: handle initialized inout port. For #1312Tristan Gingold2020-05-151-10/+12
* netlists-gates: reserve pmux and latch.Tristan Gingold2020-05-091-42/+44
* synth: add Id_Enable gate (for sequential assertions).Tristan Gingold2020-05-061-0/+1
* synth: add tri gate.Tristan Gingold2020-04-221-1/+4
* synth: rework edge handling to properly support falling edge. Fix #1227Tristan Gingold2020-04-151-5/+6
* Makefile: Generate Param_Pval_* in ghdlsynth_gates.hTristan Gingold2020-03-311-0/+10
* synth: preliminary work to export module parameters.Tristan Gingold2020-03-311-1/+2
* synth: preliminary support of multiport rams (using shared variable).Tristan Gingold2020-03-281-0/+1
* testsuite/synth: add a test for #1166Tristan Gingold2020-03-231-0/+1
* netlists: add id_nop gate.Tristan Gingold2020-03-221-0/+1
* synth: handle numeric_std minimum/maximum. Fix #1168Tristan Gingold2020-03-211-44/+48
* synthesis: handle initialized output ports.Tristan Gingold2020-03-071-7/+8
* netlists: rework memories to fix port orders, add a loop.Tristan Gingold2020-02-231-0/+2
* synth: add id_abs gate. For #1101Tristan Gingold2020-01-201-7/+8
* netlists: add dyn_insert_en gate.Tristan Gingold2019-11-111-17/+18
* ghdlsynth_gates.h: regenerate.Tristan Gingold2019-10-311-0/+4
* Regenerate ghdlsynth_gates.hTristan Gingold2019-10-211-0/+1
* Regenerate ghdlsynth_gates.hTristan Gingold2019-10-181-0/+5
* synth: regenerate ghdlsynth_gates.hTristan Gingold2019-10-031-1/+1
* synth: replace memidx2 by addidx; handle some 2d arrays.Tristan Gingold2019-10-031-1/+1
* netlists: add memidx1 and memidx2 gates.Tristan Gingold2019-10-021-4/+6
* Regenerate ghdlsynth_gates.hTristan Gingold2019-10-021-19/+24
* synth: Regenerate ghdlsynth_gates.hTristan Gingold2019-09-231-25/+26
* synth: Add support for PSL cover directive (#930)T. Meissner2019-09-191-0/+1
* synth: handle unsigned shift left.Tristan Gingold2019-09-111-50/+52
* synth: add const_sb32, add smul/umul.Tristan Gingold2019-09-071-2/+3
* synth: remove unused const gates.Tristan Gingold2019-08-301-6/+3
* synth: regenerate ghdlsynth_gates.hTristan Gingold2019-07-311-3/+4
* add port width utility function for yosys (#876)Pepijn de Vos2019-07-211-0/+3
* synth: add > and >= operators (#870)Pepijn de Vos2019-07-161-23/+24
* netlists: add assume gate.Tristan Gingold2019-07-041-0/+1
* synth: handle concurrent assertions.Tristan Gingold2019-07-021-0/+1
* ghdlsynth_gates.h: rebuild.Tristan Gingold2019-07-021-29/+33
* Add netlist generation infrastructure.Tristan Gingold2017-01-311-0/+60
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