iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	synth-vhdl_eval: handle std_logic_signed and std_logic_unsigned	Tristan Gingold	2022-09-06	1	-55/+111
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*	synth: add evaluation for ieee.std_logic_arith	Tristan Gingold	2022-09-05	1	-25/+377
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*	synth: use areapools	Tristan Gingold	2022-09-02	1	-4/+12
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*	vhdl: recognize log10 and sqrt from math_real. Fix #2176	Tristan Gingold	2022-08-14	1	-0/+14
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*	grt: add real now variable.	Tristan Gingold	2022-07-20	1	-0/+3
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*	synth-vhdl_eval: add support for more operations	Tristan Gingold	2022-06-11	1	-1/+10
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*	vhdl: recognize ieee.math_real.sign, fix is_x recogn.	Tristan Gingold	2022-06-11	1	-4/+21
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*	synth-vhdl_eval: handle more operations	Tristan Gingold	2022-06-07	1	-8/+17
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*	synth-vhdl_eval: handle more operations	Tristan Gingold	2022-06-06	1	-1/+16
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*	synth-vhdl_eval: recognize and handle to_stdulogicvector	Tristan Gingold	2022-06-06	1	-2/+4
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*	synth-vhdl_eval: handle more operations	Tristan Gingold	2022-06-05	1	-36/+110
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*	synth-vhdl_eval: handle more operations (sgn/uns reduce)	Tristan Gingold	2022-06-05	1	-6/+16
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*	synth-vhdl-eval: handle more operations	Tristan Gingold	2022-06-05	1	-24/+122
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*	synth-vhdl_eval: handle rotations and shift for numeric_std	Tristan Gingold	2022-06-05	1	-4/+40
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*	synth-vhdl_eval: handle to_x01, to_ux01, to_x01z and is_x	Tristan Gingold	2022-06-05	1	-18/+51
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*	synth-vhdl_eval: handle more operations	Tristan Gingold	2022-06-05	1	-2/+22
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*	synth-vhdl_eval: handle find_leftmost and find_rightmost	Tristan Gingold	2022-06-05	1	-0/+13
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*	synth-vhdl_eval: handle minmax	Tristan Gingold	2022-06-04	1	-66/+79
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*	synth-vhdl_eval: handle more operators (nand, nor, xnor)	Tristan Gingold	2022-06-04	1	-0/+15
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*	synth-vhdl_eval: add support for more operators.	Tristan Gingold	2022-06-04	1	-15/+59
\| \| \| \|	Fix some corner cases
*	synth-vhdl_eval: handle rotations	Tristan Gingold	2022-06-04	1	-0/+9
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*	synth-vhdl_eval: handle more operations, fix resize corner case	Tristan Gingold	2022-06-03	1	-23/+65
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*	synth-vhdl_eval: handle more operations	Tristan Gingold	2022-06-03	1	-2/+99
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*	synth-vhdl_eval: complete vector reduce operations	Tristan Gingold	2022-05-31	1	-7/+21
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*	synth-vhdl_eval: handle shift and rotations	Tristan Gingold	2022-05-31	1	-6/+29
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*	synth-vhdl_eval: handle vector match, numeric_bit.to_unsigned	Tristan Gingold	2022-05-31	1	-7/+60
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*	synth-vhdl_eval: handle more operations (to_string, match)	Tristan Gingold	2022-05-31	1	-23/+164
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*	synth-vhdl_eval: handle more operators	Tristan Gingold	2022-05-30	1	-4/+391
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*	vhdl-nodes: move maximum/minimum out of predefined operator range	Tristan Gingold	2022-05-30	1	-19/+19
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*	synth-vhdl_eval: handle more operations	Tristan Gingold	2022-05-29	1	-15/+208
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*	synth-vhdl_eval: handle resolution_limit	Tristan Gingold	2022-05-29	1	-0/+3
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*	synth-vhdl_eval: handle more operations	Tristan Gingold	2022-05-29	1	-0/+30
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*	synth-vhdl_eval: handle element-element concatenation	Tristan Gingold	2022-05-24	1	-0/+18
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*	synth-vhdl_oper: add an hook for rising_edge	Tristan Gingold	2022-05-23	1	-4/+4
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*	synth: use same elements for unbounded arrays and vectors	Tristan Gingold	2022-05-22	1	-3/+3
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*	synth: merge value for type_vector and type_array	Tristan Gingold	2022-05-22	1	-4/+4
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*	synth: use unidimentional arrays in type_acc. Factorize code.	Tristan Gingold	2022-05-22	1	-4/+5
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*	synth-vhdl_eval: handle all comparisons for enums	Tristan Gingold	2022-04-29	1	-33/+29
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*	synth-vhdl_eval: handle abs	Tristan Gingold	2022-04-27	1	-0/+2
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*	synth: renaming (synth-static_oper -> synth-vhdl_eval)	Tristan Gingold	2022-04-27	1	-0/+1060