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* update license headersumarcor2021-01-1420-220/+180
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* src/vhd: remove use of chapter sign in comment to have on ASCII charactersTristan Gingold2021-01-094-21/+21
| | | | (except for vhdl-scanner)
* vhdl: replace base_type with parent_type in nodesTristan Gingold2020-07-221-0/+1
| | | | | Only for subtype definition and remove base_type in type definitions. Allows to better track the addition of contraints.
* types: introduce Direction_Type, which replaces Iir_Direction.Tristan Gingold2020-04-204-68/+70
| | | | Global renaming.
* grt: slightly simplify the interface.Tristan Gingold2020-04-021-3/+3
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* vhdl: move get_subprogram_body_origin to vhdl-sem_inst.Tristan Gingold2020-03-241-18/+1
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* psl: keep denoting names in the PSL ast.Tristan Gingold2020-03-131-1/+2
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* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-281-0/+2
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* vhdl: remove severity from cover, report and severity from assume.Tristan Gingold2019-08-081-1/+1
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* Add support for PSL assumptions, used in formal verification (#880)Pepijn de Vos2019-08-072-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | * vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code
* simul-elaboration: rewrite assertion.Tristan Gingold2019-07-131-3/+3
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* vhdl simul-elaboration: minor rewrite.Tristan Gingold2019-07-081-3/+1
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* vhdl: rename Cover_Statement to Cover_Directive.Tristan Gingold2019-07-042-4/+4
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* ghdl_jit: almost add ghdlsynthTristan Gingold2019-06-292-234/+0
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* vhdl: move annotations from simul to vhdl.Tristan Gingold2019-06-298-1479/+6
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* synth: get rid of execution and elaboration.Tristan Gingold2019-06-192-40/+56
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* vhdl: decouple annotations from environments.Tristan Gingold2019-06-198-204/+190
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* vhdl/simulate: fix regression wrt package instances.Tristan Gingold2019-06-122-4/+6
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* simul: refine scalar type annotations.Tristan Gingold2019-06-122-17/+49
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* synth: handle integer +/- for constants.Tristan Gingold2019-06-082-2/+4
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* grt: extract grt.to_strings from grt.imagesTristan Gingold2019-06-011-9/+10
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* vhdl: differenciate block and line comments.Tristan Gingold2019-05-302-5/+5
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* vhdl/simulate: ignore some constructs for synthesis.Tristan Gingold2019-05-232-3/+5
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* Add simple_IO - to be used instead of Text_IO.Tristan Gingold2019-05-197-49/+42
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* vhdl: decouple errorouts a bit more.Tristan Gingold2019-05-101-2/+2
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* psl: add psl-types, psl-nodes_priv.Tristan Gingold2019-05-101-0/+1
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* vhdl: replace Iir_Int64 by Int64, and Iir_Fp64 by Fp64.Tristan Gingold2019-05-103-8/+7
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* Extract psl-errors from errorout.Tristan Gingold2019-05-101-1/+1
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* vhdl: extract vhdl.errors from errorout.Tristan Gingold2019-05-086-3/+6
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* vhdl: renames iirs_walk to vhdl-nodes_walkTristan Gingold2019-05-081-1/+1
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* vhdl-nodes_utils: renaming.Tristan Gingold2019-05-071-2/+2
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* vhdl: renames iir_chains to vhdl.nodes_utils. Remove iir_chain_handling.Tristan Gingold2019-05-062-2/+2
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* vhdl: move iirs_utils to vhdl.utilsTristan Gingold2019-05-066-6/+6
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* vhdl: rename iirs to vhdl.nodesTristan Gingold2019-05-058-8/+8
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* vhdl: move evaluation to vhdl child.Tristan Gingold2019-05-052-8/+8
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* vhdl: move ieee packages to vhdl children.Tristan Gingold2019-05-051-2/+2
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* vhdl: move std_standard package to vhdl child.Tristan Gingold2019-05-054-11/+11
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* vhdl: move sem* packages to vhdl children.Tristan Gingold2019-05-053-11/+11
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* vhdl: move canon to a vhdl child package.Tristan Gingold2019-05-051-2/+2
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* vhdl: move disp_tree and disp_vhdl as vhdl child.Tristan Gingold2019-05-042-5/+5
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* vhdl: move parse package as vhdl child.Tristan Gingold2019-05-041-3/+4
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* vhdl: move tokens as vhdl child package.Tristan Gingold2019-05-041-2/+2
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* vhdl: move scanner under vhdl hierarchy.Tristan Gingold2019-05-041-5/+5
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* simul: do not reverse the list twice; renaming.Tristan Gingold2019-04-161-24/+16
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* fix gnat8 errors for libghdlsynth targetsStefan Biereigel2019-03-132-3/+0
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* simul: refactoring.Tristan Gingold2019-01-112-25/+29
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* simul: handle PSL assert finalizer.Tristan Gingold2019-01-061-4/+57
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* simul: handle array values. Reformating.Tristan Gingold2018-12-291-83/+87
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* iir_kind_selected_element: use Named_Entity for homogeneity.Tristan Gingold2018-12-181-2/+2
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* Extract grt.astdio.vhdl from grt.astdio.Tristan Gingold2018-12-162-2/+3
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