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* Merge pull request #159 from YosysHQ/ecp5_pllplaceDavid Shah2018-12-012-2/+59
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| * ecp5: Pre-place PLLs and use dedicated routes into globalsDavid Shah2018-11-302-2/+59
* | Improve reporting of unknown cell typesDavid Shah2018-11-291-1/+2
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* ecp5: Fix UR PLL tile coordinatesDavid Shah2018-11-261-2/+2
* Merge pull request #143 from daveshah1/ecp5_muxesDavid Shah2018-11-265-6/+169
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| * ecp5: Add support for LUT7 muxDavid Shah2018-11-181-6/+116
| * ecp5: More optimal LUT6 placementDavid Shah2018-11-163-1/+11
| * ecp5: Adding mux support up to LUT6David Shah2018-11-163-6/+49
* | python: Fixes to get net wires map workingDavid Shah2018-11-221-2/+24
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* ecp5: Add 10% safety margin to pip delaysDavid Shah2018-11-161-2/+2
* ecp5: clangformat timing changesDavid Shah2018-11-163-17/+18
* ecp5: Use speed-grade-specific delay estimateDavid Shah2018-11-161-2/+2
* ecp5: Fix db import, improve timing data debuggingDavid Shah2018-11-163-4/+40
* ecp5: Allow selection of device speed gradeDavid Shah2018-11-161-3/+26
* ecp5: Post-rebase fixDavid Shah2018-11-161-3/+3
* ecp5: Consider fanout when calculating pip delaysDavid Shah2018-11-161-2/+12
* ecp5: Fix timing pip classesDavid Shah2018-11-161-1/+1
* ecp5: Use new timing dataDavid Shah2018-11-164-94/+82
* ecp5: Fix timing data importDavid Shah2018-11-161-5/+16
* ecp5: Adding real timing data to databaseDavid Shah2018-11-166-49/+202
* clangformatDavid Shah2018-11-162-172/+342
* Merge pull request #119 from cr1901/win-fixDavid Shah2018-11-164-2/+6
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| * Use native PATH environment-variable separator on Windows for PYTHONPATH. Fix...William D. Jones2018-11-031-0/+4
| * Rename io.{h,cc} to pio.{h,cc} to avoid naming conflict with Windows-provided...William D. Jones2018-11-033-2/+2
* | ecp5: Better use of BoostDavid Shah2018-11-161-3/+3
* | ecp5: Regression fix & formatDavid Shah2018-11-152-4/+14
* | ecp5: Support LOC attribute on DCUsDavid Shah2018-11-151-1/+25
* | ecp5: Add DCU availability checkDavid Shah2018-11-151-0/+2
* | ecp5: Add timing info for SERDESDavid Shah2018-11-151-1/+26
* | ecp5: DCU clocking fixesDavid Shah2018-11-151-2/+8
* | ecp5: EXTREFB fixesDavid Shah2018-11-152-1/+5
* | ecp5: clangformatDavid Shah2018-11-152-18/+23
* | ecp5: Trim IO connected to top level portsDavid Shah2018-11-151-15/+73
* | ecp5: Adding ancillary DCU belsDavid Shah2018-11-154-1/+57
* | ecp5: remove debug and clangformatDavid Shah2018-11-153-10/+13
* | dcu: Fix bitstream param handlingDavid Shah2018-11-151-0/+1
* | ecp5: Prefer DCCs with dedicated routing when placing DCCsDavid Shah2018-11-151-0/+43
* | ecp5: Working on DCUDavid Shah2018-11-153-5/+63
* | ecp5: DCU bitstream gen handlingDavid Shah2018-11-152-0/+299
* | ecp5: Groundwork for DCU supportDavid Shah2018-11-153-16/+318
* | Merge remote-tracking branch 'origin/master' into timingapiEddie Hung2018-11-134-3/+11
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| * \ Merge pull request #107 from YosysHQ/router_improveEddie Hung2018-11-133-2/+10
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| | * | ecp5: Improve delay estimatesDavid Shah2018-11-131-2/+2
| | * | Various router1 fixes, Add BelId/WireId/PipId::operator<()Clifford Wolf2018-11-131-0/+4
| | * | clangformatClifford Wolf2018-11-111-8/+2
| | * | Add getConflictingWireWire() arch API, streamline getConflictingXY semanticClifford Wolf2018-11-111-5/+10
| | * | Add getConflictingPipWire() arch API, router1 improvementsClifford Wolf2018-11-111-0/+5
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| * | Mark getArchOptions as override in derived classesPedro Vanzella2018-11-131-1/+1
* | | ecp5: Copy clock constraints during global promotionDavid Shah2018-11-121-0/+7
* | | timing: Add support for clock constraintsDavid Shah2018-11-121-0/+4
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