index
:
iCE40/nextpnr
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
fpga_interchange
Commit message (
Expand
)
Author
Age
Files
Lines
*
clangformat
gatecat
2022-03-09
2
-4
/
+4
*
interchange: lut map cache: remove hardcoded values
Alessandro Comodi
2022-03-04
4
-12
/
+21
*
Switch to potentially-sparse net users array
gatecat
2022-02-27
3
-22
/
+14
*
refactor: New member functions to replace design_utils
gatecat
2022-02-18
3
-5
/
+5
*
refactor: New NetInfo and CellInfo constructors
gatecat
2022-02-16
2
-6
/
+4
*
archapi: Use arbitrary rather than actual placement in predictDelay
gatecat
2021-12-19
2
-4
/
+6
*
interchange: fix uninitialized memory bug in cluster placement
Alessandro Comodi
2021-10-01
1
-1
/
+1
*
interchange: Fix compile warnings
gatecat
2021-09-28
2
-6
/
+9
*
Fix small isses and code formatting
Maciej Dudek
2021-09-27
4
-146
/
+148
*
Break up macro_cluster_placement into smaller functions
Maciej Dudek
2021-09-24
1
-20
/
+33
*
Fix AC-3 algorithm
Maciej Dudek
2021-09-23
1
-9
/
+17
*
Improve macro cluster placement
Maciej Dudek
2021-09-23
1
-235
/
+41
*
Change Cluster placement algorithm
Maciej Dudek
2021-09-23
3
-123
/
+133
*
Adding MacroCell placement
Maciej Dudek
2021-09-23
3
-17
/
+350
*
Adding support for MacroCells
Maciej Dudek
2021-09-23
4
-4
/
+382
*
interchange: xdc: add more not_implemented commands
Alessandro Comodi
2021-09-08
1
-0
/
+2
*
interchange: xdc: add common not_implemented function
Alessandro Comodi
2021-09-07
1
-5
/
+18
*
clangformat
gatecat
2021-09-06
1
-2
/
+4
*
interchange: clusters: fix other cluster allowance checks in same site
Alessandro Comodi
2021-08-31
1
-7
/
+2
*
interchange: entirely disable cache when binding site routing
Alessandro Comodi
2021-08-31
1
-6
/
+6
*
interchange: disallow placing cells on sites with clusters
Alessandro Comodi
2021-08-27
2
-4
/
+22
*
Merge pull request #780 from YosysHQ/gatecat/fix-io-inv
gatecat
2021-07-26
1
-13
/
+32
|
\
|
*
interchange: Search backwards for IO macro placements, too
gatecat
2021-07-26
1
-13
/
+32
*
|
interchange: Don't attempt to import instances as modules
gatecat
2021-07-26
1
-5
/
+0
|
/
*
interchange: Check IO validity after all are placed
gatecat
2021-07-23
1
-6
/
+16
*
Merge pull request #757 from antmicro/lut-mapping-cache
gatecat
2021-07-22
8
-74
/
+510
|
\
|
*
Added an option to disable the LUT mapping cache
Maciej Kurc
2021-07-22
5
-8
/
+16
|
*
Added more code comments, formatted the code
Maciej Kurc
2021-07-22
6
-123
/
+124
|
*
Added computing and reporting LUT mapping cache size
Maciej Kurc
2021-07-16
2
-0
/
+37
|
*
Fixed assertion typos
Maciej Kurc
2021-07-16
1
-2
/
+2
|
*
Migrated C arrays to std::array containers.
Maciej Kurc
2021-07-16
2
-9
/
+31
|
*
LUT mapping ceche optimizations 2
Maciej Kurc
2021-07-16
3
-93
/
+17
|
*
LUT mapping cache optimizations 1
Maciej Kurc
2021-07-16
2
-32
/
+48
|
*
Working site LUT mapping cache
Maciej Kurc
2021-07-16
7
-42
/
+470
*
|
Add dummy function to parse creat_clock in XDC files
Maciej Dudek
2021-07-21
1
-0
/
+7
*
|
Merge pull request #767 from YosysHQ/gatecat/ic-pref-const
gatecat
2021-07-20
1
-1
/
+10
|
\
\
|
*
|
interchange: Fix preferred constant handling when canInvert
gatecat
2021-07-20
1
-1
/
+10
*
|
|
interchange: disallow pseudo-pip on same nets if tile has luts
Alessandro Comodi
2021-07-15
1
-8
/
+18
|
/
/
*
|
[interchange] Update chipdb and python-fpga-interchange versions
Maciej Dudek
2021-07-14
1
-1
/
+1
*
|
interchange: xdc and place constr: address review comments
Alessandro Comodi
2021-07-12
2
-16
/
+13
*
|
interchange: xdc: add get_cells command
Alessandro Comodi
2021-07-12
1
-13
/
+70
*
|
interchange: add constraints constraints application routine
Alessandro Comodi
2021-07-12
3
-0
/
+106
*
|
interchange: Skip IO ports in dedicated routing check
gatecat
2021-07-12
1
-0
/
+8
*
|
interchange: Debug IO port validity check failures
gatecat
2021-07-12
2
-3
/
+5
*
|
interchange: Place DIFFINBUF and IBUFCTRL for UltraScale+ IBUFDS
gatecat
2021-07-12
1
-3
/
+4
*
|
interchange: update chipdb version
Alessandro Comodi
2021-07-08
1
-1
/
+1
*
|
interchange: reduce run-time to check dedicated interconnect
Alessandro Comodi
2021-07-08
4
-5
/
+67
|
/
*
interchange: Allow pseudo pip wires to overlap with bound site wires on the s...
gatecat
2021-07-06
2
-9
/
+5
*
interchange: Improve search for PAD-attached bels
gatecat
2021-07-06
2
-41
/
+32
*
interchange: tests: add obuftds test
Alessandro Comodi
2021-07-06
6
-0
/
+80
[next]