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* Merge pull request #780 from YosysHQ/gatecat/fix-io-invgatecat2021-07-261-13/+32
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| * interchange: Search backwards for IO macro placements, toogatecat2021-07-261-13/+32
* | interchange: Don't attempt to import instances as modulesgatecat2021-07-261-5/+0
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* interchange: Check IO validity after all are placedgatecat2021-07-231-6/+16
* Merge pull request #757 from antmicro/lut-mapping-cachegatecat2021-07-228-74/+510
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| * Added an option to disable the LUT mapping cacheMaciej Kurc2021-07-225-8/+16
| * Added more code comments, formatted the codeMaciej Kurc2021-07-226-123/+124
| * Added computing and reporting LUT mapping cache sizeMaciej Kurc2021-07-162-0/+37
| * Fixed assertion typosMaciej Kurc2021-07-161-2/+2
| * Migrated C arrays to std::array containers.Maciej Kurc2021-07-162-9/+31
| * LUT mapping ceche optimizations 2Maciej Kurc2021-07-163-93/+17
| * LUT mapping cache optimizations 1Maciej Kurc2021-07-162-32/+48
| * Working site LUT mapping cacheMaciej Kurc2021-07-167-42/+470
* | Add dummy function to parse creat_clock in XDC filesMaciej Dudek2021-07-211-0/+7
* | Merge pull request #767 from YosysHQ/gatecat/ic-pref-constgatecat2021-07-201-1/+10
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| * | interchange: Fix preferred constant handling when canInvertgatecat2021-07-201-1/+10
* | | interchange: disallow pseudo-pip on same nets if tile has lutsAlessandro Comodi2021-07-151-8/+18
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* | [interchange] Update chipdb and python-fpga-interchange versionsMaciej Dudek2021-07-141-1/+1
* | interchange: xdc and place constr: address review commentsAlessandro Comodi2021-07-122-16/+13
* | interchange: xdc: add get_cells commandAlessandro Comodi2021-07-121-13/+70
* | interchange: add constraints constraints application routineAlessandro Comodi2021-07-123-0/+106
* | interchange: Skip IO ports in dedicated routing checkgatecat2021-07-121-0/+8
* | interchange: Debug IO port validity check failuresgatecat2021-07-122-3/+5
* | interchange: Place DIFFINBUF and IBUFCTRL for UltraScale+ IBUFDSgatecat2021-07-121-3/+4
* | interchange: update chipdb versionAlessandro Comodi2021-07-081-1/+1
* | interchange: reduce run-time to check dedicated interconnectAlessandro Comodi2021-07-084-5/+67
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* interchange: Allow pseudo pip wires to overlap with bound site wires on the s...gatecat2021-07-062-9/+5
* interchange: Improve search for PAD-attached belsgatecat2021-07-062-41/+32
* interchange: tests: add obuftds testAlessandro Comodi2021-07-066-0/+80
* interchange: phys: skip only nets writing on disconnected out portsAlessandro Comodi2021-07-021-2/+13
* Merge pull request #746 from YosysHQ/gatecat/ic-can-invert-constgatecat2021-07-011-5/+9
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| * interchange: Handle canInvert PIPs when processing preferred constantsgatecat2021-07-011-5/+9
* | interchange: Handle case where routing source is a nodegatecat2021-07-011-0/+5
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* Merge pull request #744 from YosysHQ/gatecat/const-in-macrogatecat2021-07-011-1/+1
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| * interchange: Fix handling of constants in macrosgatecat2021-07-011-1/+1
* | Merge pull request #743 from YosysHQ/gatecat/site-rsv-portsgatecat2021-07-015-0/+69
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| * | interchange: Reserve site ports only reachable from dedicated routinggatecat2021-07-015-0/+69
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* / interchange: phys: do not output nets which have no usersAlessandro Comodi2021-07-011-1/+12
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* interchange: fix dedicated interconnect explorationAlessandro Comodi2021-06-301-8/+14
* interchange: Fix dedicated interconnect check when site is the samegatecat2021-06-301-1/+4
* interchange: Place IO macro content based on routinggatecat2021-06-301-0/+79
* interchange: Track the macros that cells have been expanded fromgatecat2021-06-293-0/+8
* Merge pull request #736 from YosysHQ/gatecat/pp-multi-outputgatecat2021-06-281-13/+2
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| * interchange: Allow site wires driven by more than one belgatecat2021-06-281-13/+2
* | interchange: Handle disconnected bel pins in dedicated interconnectgatecat2021-06-281-1/+1
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* interchange: arch: move macro expansion step before ios packingAlessandro Comodi2021-06-181-1/+1
* Merge pull request #728 from YosysHQ/gatecat/nexus-ramgatecat2021-06-156-0/+382
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| * nexus: Add modified version of RAM testgatecat2021-06-155-0/+206
| * nexus: Add PDPSC16K->PDPSC16K_MODE to remap rulesgatecat2021-06-151-0/+176
* | interchange: fix phys net writerAlessandro Comodi2021-06-151-5/+2
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