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fpga_interchange
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Merge pull request #780 from YosysHQ/gatecat/fix-io-inv
gatecat
2021-07-26
1
-13
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+32
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interchange: Search backwards for IO macro placements, too
gatecat
2021-07-26
1
-13
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+32
*
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interchange: Don't attempt to import instances as modules
gatecat
2021-07-26
1
-5
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+0
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interchange: Check IO validity after all are placed
gatecat
2021-07-23
1
-6
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+16
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Merge pull request #757 from antmicro/lut-mapping-cache
gatecat
2021-07-22
8
-74
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+510
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Added an option to disable the LUT mapping cache
Maciej Kurc
2021-07-22
5
-8
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+16
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Added more code comments, formatted the code
Maciej Kurc
2021-07-22
6
-123
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+124
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Added computing and reporting LUT mapping cache size
Maciej Kurc
2021-07-16
2
-0
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+37
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Fixed assertion typos
Maciej Kurc
2021-07-16
1
-2
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+2
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Migrated C arrays to std::array containers.
Maciej Kurc
2021-07-16
2
-9
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+31
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LUT mapping ceche optimizations 2
Maciej Kurc
2021-07-16
3
-93
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+17
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LUT mapping cache optimizations 1
Maciej Kurc
2021-07-16
2
-32
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+48
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Working site LUT mapping cache
Maciej Kurc
2021-07-16
7
-42
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+470
*
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Add dummy function to parse creat_clock in XDC files
Maciej Dudek
2021-07-21
1
-0
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+7
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Merge pull request #767 from YosysHQ/gatecat/ic-pref-const
gatecat
2021-07-20
1
-1
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+10
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interchange: Fix preferred constant handling when canInvert
gatecat
2021-07-20
1
-1
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+10
*
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interchange: disallow pseudo-pip on same nets if tile has luts
Alessandro Comodi
2021-07-15
1
-8
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+18
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[interchange] Update chipdb and python-fpga-interchange versions
Maciej Dudek
2021-07-14
1
-1
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+1
*
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interchange: xdc and place constr: address review comments
Alessandro Comodi
2021-07-12
2
-16
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+13
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interchange: xdc: add get_cells command
Alessandro Comodi
2021-07-12
1
-13
/
+70
*
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interchange: add constraints constraints application routine
Alessandro Comodi
2021-07-12
3
-0
/
+106
*
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interchange: Skip IO ports in dedicated routing check
gatecat
2021-07-12
1
-0
/
+8
*
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interchange: Debug IO port validity check failures
gatecat
2021-07-12
2
-3
/
+5
*
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interchange: Place DIFFINBUF and IBUFCTRL for UltraScale+ IBUFDS
gatecat
2021-07-12
1
-3
/
+4
*
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interchange: update chipdb version
Alessandro Comodi
2021-07-08
1
-1
/
+1
*
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interchange: reduce run-time to check dedicated interconnect
Alessandro Comodi
2021-07-08
4
-5
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+67
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interchange: Allow pseudo pip wires to overlap with bound site wires on the s...
gatecat
2021-07-06
2
-9
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+5
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interchange: Improve search for PAD-attached bels
gatecat
2021-07-06
2
-41
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+32
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interchange: tests: add obuftds test
Alessandro Comodi
2021-07-06
6
-0
/
+80
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interchange: phys: skip only nets writing on disconnected out ports
Alessandro Comodi
2021-07-02
1
-2
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+13
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Merge pull request #746 from YosysHQ/gatecat/ic-can-invert-const
gatecat
2021-07-01
1
-5
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+9
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interchange: Handle canInvert PIPs when processing preferred constants
gatecat
2021-07-01
1
-5
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+9
*
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interchange: Handle case where routing source is a node
gatecat
2021-07-01
1
-0
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+5
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Merge pull request #744 from YosysHQ/gatecat/const-in-macro
gatecat
2021-07-01
1
-1
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+1
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interchange: Fix handling of constants in macros
gatecat
2021-07-01
1
-1
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+1
*
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Merge pull request #743 from YosysHQ/gatecat/site-rsv-ports
gatecat
2021-07-01
5
-0
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+69
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interchange: Reserve site ports only reachable from dedicated routing
gatecat
2021-07-01
5
-0
/
+69
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interchange: phys: do not output nets which have no users
Alessandro Comodi
2021-07-01
1
-1
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+12
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interchange: fix dedicated interconnect exploration
Alessandro Comodi
2021-06-30
1
-8
/
+14
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interchange: Fix dedicated interconnect check when site is the same
gatecat
2021-06-30
1
-1
/
+4
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interchange: Place IO macro content based on routing
gatecat
2021-06-30
1
-0
/
+79
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interchange: Track the macros that cells have been expanded from
gatecat
2021-06-29
3
-0
/
+8
*
Merge pull request #736 from YosysHQ/gatecat/pp-multi-output
gatecat
2021-06-28
1
-13
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+2
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interchange: Allow site wires driven by more than one bel
gatecat
2021-06-28
1
-13
/
+2
*
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interchange: Handle disconnected bel pins in dedicated interconnect
gatecat
2021-06-28
1
-1
/
+1
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interchange: arch: move macro expansion step before ios packing
Alessandro Comodi
2021-06-18
1
-1
/
+1
*
Merge pull request #728 from YosysHQ/gatecat/nexus-ram
gatecat
2021-06-15
6
-0
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+382
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nexus: Add modified version of RAM test
gatecat
2021-06-15
5
-0
/
+206
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nexus: Add PDPSC16K->PDPSC16K_MODE to remap rules
gatecat
2021-06-15
1
-0
/
+176
*
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interchange: fix phys net writer
Alessandro Comodi
2021-06-15
1
-5
/
+2
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