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* ice40: Lock out mutually exclusive pipsDavid Shah2018-06-101-2/+12
* ice40: Writing an empty ASC fileDavid Shah2018-06-101-0/+1
* ice40: Adding non-routing config bits to databaseDavid Shah2018-06-101-8/+8
* ice40: Add switch data to databaseDavid Shah2018-06-101-0/+48
* Getting rid of .nil() methods, compare with zero- and default-constructed obj...Clifford Wolf2018-06-091-32/+26
* Add very basic routerClifford Wolf2018-06-091-13/+93
* Applied clang-format to my own contributionsZipCPU2018-06-071-6/+11
* Set the default log to stdoutZipCPU2018-06-071-1/+12
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| * Initial (random) placer capabilityZipCPU2018-06-071-1/+12
* | ice40: Refactor PortPin and add Python bindingDavid Shah2018-06-071-107/+4
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* clang-format for design and chip codebaseClifford Wolf2018-06-071-439/+440
* Add ice40 geometry informationClifford Wolf2018-06-061-1/+6
* Add ice40 --test modeClifford Wolf2018-06-061-0/+9
* Refactor Chip API and iCE40 databaseClifford Wolf2018-06-061-119/+231
* Add iCE40 blockram belsClifford Wolf2018-06-041-0/+84
* Replace GuiLine with GraphicElementClifford Wolf2018-06-041-7/+4
* Add iCE40 SB_IO belsClifford Wolf2018-06-031-2/+15
* Add ice40 ICESTORM_LC belsClifford Wolf2018-06-021-3/+22
* Use singular in type names (BelRange, WireIterator)Clifford Wolf2018-06-021-18/+18
* Add DelayInfo structClifford Wolf2018-05-291-2/+10
* Progress in chip.h APIClifford Wolf2018-05-261-28/+110
* Progress in ice40 chipdbClifford Wolf2018-05-261-48/+115
* Start work on iCE40 chipdbClifford Wolf2018-05-261-0/+224
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