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ice40
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chip.h
Commit message (
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)
Author
Age
Files
Lines
*
ice40: Only place IO at valid pins
David Shah
2018-06-16
1
-0
/
+1
*
Add route-ripup routing loop
Clifford Wolf
2018-06-14
1
-6
/
+12
*
Refactor position/delay estimation API
Clifford Wolf
2018-06-14
1
-9
/
+2
*
Add hierarchy to bel/wire/pip names
Clifford Wolf
2018-06-13
1
-10
/
+1
*
Update chip Graphics API
Clifford Wolf
2018-06-13
1
-1
/
+7
*
Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr
Clifford Wolf
2018-06-13
1
-1
/
+19
|
\
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*
ice40: Add a PCF parser
David Shah
2018-06-13
1
-0
/
+2
|
*
ice40: Add package selection
David Shah
2018-06-13
1
-0
/
+1
|
*
ice40: Add package pins to database
David Shah
2018-06-13
1
-1
/
+16
*
|
Redesign PosInfo API
Clifford Wolf
2018-06-13
1
-3
/
+11
|
/
*
Add fast IdString <-> PortPin conversion
Clifford Wolf
2018-06-12
1
-0
/
+1
*
Add IdString API
Clifford Wolf
2018-06-12
1
-3
/
+6
*
Fix NEXTPNR_NAMESPACE
Clifford Wolf
2018-06-12
1
-6
/
+6
*
Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr
Clifford Wolf
2018-06-12
1
-0
/
+2
|
\
|
*
ice40: Adding a placement validity checker
David Shah
2018-06-12
1
-0
/
+2
*
|
Add nextpnr namespace
Clifford Wolf
2018-06-12
1
-6
/
+14
|
/
*
Add "nextpnr.h"
Clifford Wolf
2018-06-11
1
-2
/
+4
*
Remove pool, dict, vector namespace aliases
Clifford Wolf
2018-06-11
1
-15
/
+15
*
Add conflicting=false argument to bind getters
Clifford Wolf
2018-06-11
1
-3
/
+4
*
Pass design to gui, display chip name
Miodrag Milanovic
2018-06-10
1
-0
/
+2
*
Improving 5k support
David Shah
2018-06-10
1
-0
/
+5
*
Add support for iCE40 global buffers (currently only for 1k devices)
Clifford Wolf
2018-06-10
1
-1
/
+2
*
Fix ice40 pip/switch locked performance issue
Clifford Wolf
2018-06-10
1
-14
/
+7
*
ice40: Add IO config to bitstream
David Shah
2018-06-10
1
-3
/
+12
*
ice40: Lock out mutually exclusive pips
David Shah
2018-06-10
1
-2
/
+12
*
ice40: Writing an empty ASC file
David Shah
2018-06-10
1
-0
/
+1
*
ice40: Adding non-routing config bits to database
David Shah
2018-06-10
1
-8
/
+8
*
ice40: Add switch data to database
David Shah
2018-06-10
1
-0
/
+48
*
Getting rid of .nil() methods, compare with zero- and default-constructed obj...
Clifford Wolf
2018-06-09
1
-32
/
+26
*
Add very basic router
Clifford Wolf
2018-06-09
1
-13
/
+93
*
Applied clang-format to my own contributions
ZipCPU
2018-06-07
1
-6
/
+11
*
Set the default log to stdout
ZipCPU
2018-06-07
1
-1
/
+12
|
\
|
*
Initial (random) placer capability
ZipCPU
2018-06-07
1
-1
/
+12
*
|
ice40: Refactor PortPin and add Python binding
David Shah
2018-06-07
1
-107
/
+4
|
/
*
clang-format for design and chip codebase
Clifford Wolf
2018-06-07
1
-439
/
+440
*
Add ice40 geometry information
Clifford Wolf
2018-06-06
1
-1
/
+6
*
Add ice40 --test mode
Clifford Wolf
2018-06-06
1
-0
/
+9
*
Refactor Chip API and iCE40 database
Clifford Wolf
2018-06-06
1
-119
/
+231
*
Add iCE40 blockram bels
Clifford Wolf
2018-06-04
1
-0
/
+84
*
Replace GuiLine with GraphicElement
Clifford Wolf
2018-06-04
1
-7
/
+4
*
Add iCE40 SB_IO bels
Clifford Wolf
2018-06-03
1
-2
/
+15
*
Add ice40 ICESTORM_LC bels
Clifford Wolf
2018-06-02
1
-3
/
+22
*
Use singular in type names (BelRange, WireIterator)
Clifford Wolf
2018-06-02
1
-18
/
+18
*
Add DelayInfo struct
Clifford Wolf
2018-05-29
1
-2
/
+10
*
Progress in chip.h API
Clifford Wolf
2018-05-26
1
-28
/
+110
*
Progress in ice40 chipdb
Clifford Wolf
2018-05-26
1
-48
/
+115
*
Start work on iCE40 chipdb
Clifford Wolf
2018-05-26
1
-0
/
+224