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* Merge pull request #1438 from YosysHQ/eddie/xilinx_dsp_commentsEddie Hung2019-10-085-72/+364
|\ | | | | Add notes and comments for xilinx_dsp
| * Missed thisEddie Hung2019-10-051-3/+4
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| * Add comment on why we have to match for clock-enable/reset muxesEddie Hung2019-10-053-3/+11
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| * Add note on pattern detectorEddie Hung2019-10-051-3/+7
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| * Add comment on why partial multipliers are 18x18Eddie Hung2019-10-041-4/+8
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| * Add comments for xilinx_dsp_cascadeEddie Hung2019-10-041-12/+100
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| * Improve comments for xilinx_dsp_CREGEddie Hung2019-10-041-6/+7
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| * Fix commentEddie Hung2019-10-041-1/+1
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| * Restore optimisation for sigM.empty()Eddie Hung2019-10-041-1/+4
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| * Retry on fixing TODOsEddie Hung2019-10-042-13/+1
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| * Revert "Fix TODOs"Eddie Hung2019-10-042-0/+20
| | | | | | | | This reverts commit 8674a6c68d563908014d16671567459499c6dc99.
| * More comments, cleanupEddie Hung2019-10-042-41/+108
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| * Fix TODOsEddie Hung2019-10-042-20/+0
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| * ConsistencyEddie Hung2019-10-041-3/+3
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| * Add comments for xilinx_dspEddie Hung2019-10-043-6/+134
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* | Merge pull request #1439 from YosysHQ/eddie/fix_ice40_wrapcarryClifford Wolf2019-10-062-0/+26
|\ \ | | | | | | Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf
| * | Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolfEddie Hung2019-10-052-0/+26
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* | Update README.mdClifford Wolf2019-10-051-1/+1
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* | Merge pull request #1436 from YosysHQ/mmicko/msvc_fixMiodrag Milanović2019-10-052-2/+7
|\ \ | |/ |/| Fixes for MSVC build
| * Fixes for MSVC buildMiodrag Milanovic2019-10-042-2/+7
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* | Fix typo in check_label()Eddie Hung2019-10-041-1/+1
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* | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`Eddie Hung2019-10-042-5/+19
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* | Remove DSP48E1 from *_cells_xtra.vEddie Hung2019-10-043-178/+2
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* | Fix xilinx_dsp for unsigned extensionsEddie Hung2019-10-041-1/+3
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* | Fix for SigSpec() == SigSpec(State::Sx, 0) to be true againEddie Hung2019-10-041-0/+6
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* | Add Const::{begin,end,empty}()Eddie Hung2019-10-041-0/+3
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* | Panic over. Model was elsewhere. Re-arrange for consistencyEddie Hung2019-10-045-31/+4
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* | OopsEddie Hung2019-10-041-1/+1
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* | Ohmilord this wasn't added all this time!?!Eddie Hung2019-10-041-0/+29
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* Change smtbmc "Warmup failed" status to "PREUNSAT"Clifford Wolf2019-10-031-14/+14
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Update ABC to git rev 623b5e8Clifford Wolf2019-10-031-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Bump versionClifford Wolf2019-10-031-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #1419 from YosysHQ/eddie/lazy_deriveClifford Wolf2019-10-032-35/+59
|\ | | | | module->derive() to be lazy and not touch ast if already derived
| * Fix for svinterfacesEddie Hung2019-09-301-2/+8
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| * module->derive() to be lazy and not touch ast if already derivedEddie Hung2019-09-302-33/+51
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* | Merge pull request #1422 from YosysHQ/eddie/aigmap_selectClifford Wolf2019-10-032-6/+50
|\ \ | | | | | | Add -select option to aigmap
| * | Add quick testEddie Hung2019-09-301-0/+10
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| * | Add -select option to aigmapEddie Hung2019-09-301-6/+40
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* | | Merge pull request #1429 from YosysHQ/clifford/checkmappedClifford Wolf2019-10-032-27/+56
|\ \ \ | | | | | | | | Add "check -mapped"
| * | | Add "check -allow-tbuf"Clifford Wolf2019-10-031-8/+22
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Add "check -mapped"Clifford Wolf2019-10-022-21/+36
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge pull request #1425 from YosysHQ/dave/ecp5_pdp16David Shah2019-10-036-2/+184
|\ \ \ \ | | | | | | | | | | ecp5: Add support for mapping 36-bit wide PDP BRAMs
| * | | | ecp5: Fix shuffle_enable portDavid Shah2019-10-011-2/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | ecp5: Add support for mapping 36-bit wide PDP BRAMsDavid Shah2019-10-016-1/+183
| | |/ / | |/| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | Merge pull request #1423 from YosysHQ/eddie/techmap_replace_wireEddie Hung2019-10-022-0/+32
|\ \ \ \ | | | | | | | | | | RFC: techmap to recognise wires named "_TECHMAP_REPLACE_.<suffix>"
| * | | | Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolfEddie Hung2019-10-021-4/+8
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| * | | | Extend test with renaming cells with prefix tooEddie Hung2019-10-021-0/+2
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| * | | | Add testEddie Hung2019-09-301-0/+16
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| * | | | techmap wires named _TECHMAP_REPLACE_.<identifier> to create aliasEddie Hung2019-09-301-0/+10
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* | | | log_dump() to support State enumEddie Hung2019-10-023-0/+6
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