| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | shiftx NULL pointer check | Eddie Hung | 2019-03-18 | 1 | -8/+10 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | Cleanup | Eddie Hung | 2019-03-16 | 1 | -35/+25 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | Only accept <128 for variable length, only if $shiftx exclusive | Eddie Hung | 2019-03-16 | 2 | -13/+18 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | Cleanup synth_xilinx | Eddie Hung | 2019-03-15 | 2 | -3/+2 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | Working | Eddie Hung | 2019-03-15 | 3 | -274/+434 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | Reverse bits in INIT parameter for Xilinx, since MSB is shifted first | Eddie Hung | 2019-03-14 | 1 | -16/+32 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | Misspell | Eddie Hung | 2019-03-14 | 1 | -1/+1 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | Revert "Add shregmap -init_msb_first and use in synth_xilinx" | Eddie Hung | 2019-03-14 | 2 | -17/+4 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 26ecbc1aee1dca1c186ab2b51835d74f67bc3e75. | |||||
| | * | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7srl | Eddie Hung | 2019-03-14 | 82 | -584/+2483 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Add shregmap -init_msb_first and use in synth_xilinx | Eddie Hung | 2019-03-14 | 2 | -4/+16 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Fix cells_map for SRL | Eddie Hung | 2019-03-14 | 1 | -19/+17 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Move shregmap until after first techmap | Eddie Hung | 2019-03-13 | 1 | -2/+2 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor $__SHREG__ in cells_map.v | Eddie Hung | 2019-03-13 | 1 | -32/+24 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Remove SRL16/32 from cells_xtra | Eddie Hung | 2019-02-28 | 2 | -18/+2 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Add SRL16 and SRL32 sim models | Eddie Hung | 2019-02-28 | 1 | -0/+39 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Fix SRL16/32 techmap off-by-one | Eddie Hung | 2019-02-28 | 1 | -18/+24 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | synth_xilinx to call shregmap with enable support | Eddie Hung | 2019-02-28 | 2 | -24/+29 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | synth_xilinx to use shregmap with -params too | Eddie Hung | 2019-02-28 | 2 | -22/+19 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | synth_xilinx to now have shregmap call after dff2dffe | Eddie Hung | 2019-02-28 | 1 | -0/+2 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Add techmap rule for $__SHREG_DFF_P_ to SRL16/32 | Eddie Hung | 2019-02-28 | 1 | -0/+71 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | Add MUXCY and XORCY to cells_box.v | Eddie Hung | 2019-04-16 | 2 | -0/+15 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | Fix wire numbering | Eddie Hung | 2019-04-16 | 1 | -1/+2 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | Do not put constants into output_bits | Eddie Hung | 2019-04-16 | 1 | -2/+2 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | Remove write_verilog call | Eddie Hung | 2019-04-16 | 1 | -1/+1 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | Fix spacing | Eddie Hung | 2019-04-16 | 2 | -2/+2 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'xaig' into xc7mux | Eddie Hung | 2019-04-16 | 2 | -3/+1 | |
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / / / / / / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | | | | | | | | | | | | | | Re-enable partsel.v test | Eddie Hung | 2019-04-16 | 1 | -1/+0 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | abc9 to call "setundef -zero" behaving as for abc | Eddie Hung | 2019-04-16 | 1 | -0/+3 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | NULL check before use | Eddie Hung | 2019-04-16 | 1 | -1/+1 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | WIP for box support | Eddie Hung | 2019-04-16 | 1 | -36/+93 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | ABC to read_box before reading netlist | Eddie Hung | 2019-04-16 | 1 | -1/+3 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | Make cells.box whiteboxes not blackboxes | Eddie Hung | 2019-04-16 | 1 | -2/+2 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | read_verilog cells_box.v before techmap | Eddie Hung | 2019-04-16 | 1 | -1/+1 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | synth_xilinx: before abc read +/xilinx/cells_box.v | Eddie Hung | 2019-04-16 | 1 | -0/+1 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | Add +/xilinx/cells_box.v containing models for ABC boxes | Eddie Hung | 2019-04-16 | 2 | -0/+11 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | For 'stat' do not count modules with abc_box_id | Eddie Hung | 2019-04-16 | 1 | -0/+3 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | Do not call abc on modules with abc_box_id attr | Eddie Hung | 2019-04-16 | 1 | -0/+3 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | Revert "Add abc_box_id attribute to MUXF7/F8 cells" | Eddie Hung | 2019-04-16 | 1 | -2/+0 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 8fbbd9b129697152c93c35831c1d50982702a3ec. | |||||
| * | | | | | | | | | | | | | | | | | | | | | | | | | | Use abc_box_id | Eddie Hung | 2019-04-15 | 1 | -2/+1 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | Check abc_box_id attr | Eddie Hung | 2019-04-15 | 1 | -1/+16 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | Add abc_box_id attribute to MUXF7/F8 cells | Eddie Hung | 2019-04-15 | 1 | -0/+2 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'xaig' into xc7mux | Eddie Hung | 2019-04-15 | 9 | -100/+246 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-15 | 3 | -6/+5 | |
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | |_|_|_|_|_|_|_|/ / / / / / / / / / / / / / / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | ||||||
| | | * | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #937 from YosysHQ/revert-932-eddie/fixdlatch | Eddie Hung | 2019-04-15 | 2 | -4/+3 | |
| | | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Revert "Recognise default entry in case even if all cases covered (fix for #931)" | |||||
| | | | * | | | | | | | | | | | | | | | | | | | | | | | | Revert "Recognise default entry in case even if all cases covered (fix for ↵ | Eddie Hung | 2019-04-15 | 2 | -4/+3 | |
| | | |/ / / / / / / / / / / / / / / / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | #931)" | |||||
| | | * | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #936 from YosysHQ/README-fix-quotes | Eddie Hung | 2019-04-15 | 1 | -2/+2 | |
| | | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | |_|_|_|_|_|_|_|_|_|_|_|_|/ / / / / / / / / / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | README: fix some incorrect quoting | |||||
| | | | * | | | | | | | | | | | | | | | | | | | | | | | README: fix some incorrect quoting. | whitequark | 2019-04-15 | 1 | -2/+2 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | Forgot backslashes | Eddie Hung | 2019-04-12 | 1 | -1/+1 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | Handle __dummy_o__ and __const[01]__ in read_aiger not abc | Eddie Hung | 2019-04-12 | 2 | -18/+8 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | abc to ignore __dummy_o__ and __const[01]__ when re-integrating | Eddie Hung | 2019-04-12 | 1 | -6/+20 | |
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index : iCE40/yosys | |
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