| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | | * | | | | Add citation | Eddie Hung | 2019-11-26 | 1 | -0/+1 | |
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| | | * | | | | Check for either sign or zero extension for postAdd packing | Eddie Hung | 2019-11-26 | 1 | -3/+3 | |
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| | | * | | | | Add testcase derived from fastfir_dynamictaps benchmark | Eddie Hung | 2019-11-26 | 1 | -0/+68 | |
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| | * | | | | Merge pull request #1501 from YosysHQ/dave/mem_copy_attr | Clifford Wolf | 2019-11-27 | 1 | -0/+4 | |
| | |\ \ \ \ | | | | | | | | | | | | | memory_collect: Copy attr from RTLIL::Memory to cell | |||||
| | | * | | | | memory_collect: Copy attr from RTLIL::Memory to cell | David Shah | 2019-11-18 | 1 | -0/+4 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | * | | | | | Merge pull request #1534 from YosysHQ/mwk/opt_share-fix | Clifford Wolf | 2019-11-27 | 2 | -4/+24 | |
| | |\ \ \ \ \ | | | | | | | | | | | | | | | opt_share: Fix handling of fine cells. | |||||
| | | * | | | | | opt_share: Fix handling of fine cells. | Marcin Kościelnicki | 2019-11-27 | 2 | -4/+24 | |
| | | | |/ / / | | |/| | | | | | | | | | | | | | | | Fixes #1525. | |||||
| | * | | | | | Merge pull request #1535 from YosysHQ/eddie/write_xaiger_improve | Eddie Hung | 2019-11-27 | 2 | -22/+5 | |
| | |\ \ \ \ \ | | |/ / / / | |/| | | | | write_xaiger improvements | |||||
| * | | | | | | ean call after abc{,9} | Eddie Hung | 2019-11-27 | 1 | -1/+2 | |
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| * | | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-27 | 1 | -7/+3 | |
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| | * | | | | | Do not replace constants with same wire | Eddie Hung | 2019-11-27 | 1 | -7/+3 | |
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| * | | | | | | Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff | Eddie Hung | 2019-11-27 | 4 | -34/+30 | |
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| | * | | | | | latch -> box | Eddie Hung | 2019-11-26 | 1 | -1/+1 | |
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| | * | | | | | Remove notes | Eddie Hung | 2019-11-26 | 1 | -9/+0 | |
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| | * | | | | | Fold loop | Eddie Hung | 2019-11-26 | 1 | -6/+3 | |
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| | * | | | | | Do not sigmap keep bits inside write_xaiger | Eddie Hung | 2019-11-26 | 1 | -1/+1 | |
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| | * | | | | | xaiger: do not promote output wires | Eddie Hung | 2019-11-26 | 1 | -5/+0 | |
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| | * | | | | xilinx: Add simulation models for IOBUF and OBUFT. | Marcin Kościelnicki | 2019-11-26 | 3 | -25/+30 | |
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| * | | | | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-27 | 0 | -0/+0 | |
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| | * | | | | | clkpart to analyse async flops too | Eddie Hung | 2019-11-25 | 1 | -0/+8 | |
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| * | | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-27 | 2 | -49/+94 | |
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| | * | | | | | Cleanup | Eddie Hung | 2019-11-27 | 1 | -5/+3 | |
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| | * | | | | | Check for nullptr | Eddie Hung | 2019-11-27 | 1 | -1/+1 | |
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| | * | | | | | Stray log_dump | Eddie Hung | 2019-11-27 | 1 | -1/+0 | |
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| | * | | | | | Revert "submod to bitty rather bussy, for bussy wires used as input and output" | Eddie Hung | 2019-11-27 | 2 | -42/+76 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit cba3073026711e7683c46ba091c56a5c5a041a45. | |||||
| | * | | | | | Promote output wires in sigmap so that can be detected | Eddie Hung | 2019-11-26 | 1 | -8/+4 | |
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| | * | | | | | Fix wire width | Eddie Hung | 2019-11-26 | 1 | -2/+2 | |
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| | * | | | | | Fix submod -hidden | Eddie Hung | 2019-11-26 | 1 | -5/+6 | |
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| | * | | | | | Add -hidden option to submod | Eddie Hung | 2019-11-26 | 1 | -11/+25 | |
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| | * | | | | | Update docs with bullet points | Eddie Hung | 2019-11-26 | 1 | -10/+9 | |
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| | * | | | | | Move \init from source wire to submod if output port | Eddie Hung | 2019-11-25 | 1 | -0/+7 | |
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| | * | | | | | Add testcase where \init is copied | Eddie Hung | 2019-11-25 | 1 | -0/+18 | |
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| * | | | | | | Merge branch 'master' into xaig_dff | Eddie Hung | 2019-11-26 | 0 | -0/+0 | |
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| | * \ \ \ \ \ | Merge branch 'master' of github.com:YosysHQ/yosys | Eddie Hung | 2019-11-22 | 312 | -25148/+44916 | |
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| | * | | | | | | | Fix typo | Eddie Hung | 2019-09-27 | 1 | -1/+1 | |
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| * | | | | | | | | xaiger: do not promote output wires | Eddie Hung | 2019-11-26 | 1 | -5/+0 | |
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| * | | | | | | | | Move 'clean' from map_luts to finalize | Eddie Hung | 2019-11-26 | 1 | -1/+1 | |
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| * | | | | | | | | Fix submod -hidden | Eddie Hung | 2019-11-26 | 1 | -5/+6 | |
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| * | | | | | | | | clkpart to use 'submod -hidden' | Eddie Hung | 2019-11-26 | 1 | -1/+1 | |
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| * | | | | | | | | Add -hidden option to submod | Eddie Hung | 2019-11-26 | 1 | -20/+40 | |
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| * | | | | | | | | Fold loop | Eddie Hung | 2019-11-25 | 1 | -6/+3 | |
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| * | | | | | | | | Do not sigmap keep bits inside write_xaiger | Eddie Hung | 2019-11-25 | 1 | -1/+1 | |
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| * | | | | | | | | Fix debug | Eddie Hung | 2019-11-25 | 1 | -3/+3 | |
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| * | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-25 | 10 | -18/+83 | |
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| | * | | | | | | | clkbufmap: Add support for inverters in clock path. | Marcin Kościelnicki | 2019-11-25 | 4 | -6/+69 | |
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| | * | | | | | | | xilinx: Use INV instead of LUT1 when applicable | Marcin Kościelnicki | 2019-11-25 | 5 | -10/+14 | |
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| | * | | | | | | Merge pull request #1520 from pietrmar/fix-1463 | Eddie Hung | 2019-11-22 | 1 | -2/+0 | |
| | |\ \ \ \ \ \ | | |_|/ / / / | |/| | | | | | coolrunner2: remove spurious log_pop() call, fixes #1463 | |||||
| | | * | | | | | coolrunner2: remove spurious log_pop() call, fixes #1463 | Martin Pietryka | 2019-11-23 | 1 | -2/+0 | |
| | |/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was causing a segmentation fault because there is no accompanying log_push() call so header_count.size() became -1. Signed-off-by: Martin Pietryka <martin@pietryka.at> | |||||
| * | | | | | | Special abc9_clock wire to contain only clock signal | Eddie Hung | 2019-11-25 | 1 | -12/+10 | |
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| * | | | | | | abc9 to contain time call | Eddie Hung | 2019-11-25 | 1 | -1/+1 | |
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index : iCE40/yosys | |
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