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* proc_clean: add -quiet option.whitequark2019-07-091-8/+24
| | | | This is useful for other passes that call it often, like bugpoint.
* Merge pull request #1159 from btut/fix/1090_segfault_cell_and_wireClifford Wolf2019-07-051-0/+3
|\ | | | | Throw runtime exception when trying to convert inexistend C++ object to Python
| * Throw runtime exception when trying to convert a c++-pointer to aBenedikt Tutzer2019-07-041-0/+3
|/ | | | | | python-object in case the pointer is a nullptr to avoid a segfault. Fixes #1090
* Merge pull request #1156 from YosysHQ/eddie/fix_abc9_unknown_cellEddie Hung2019-07-033-6/+28
|\ | | | | write_xaiger to treat unknown cell connections as keep-s
| * write_xaiger to treat unknown cell connections as keep-sEddie Hung2019-07-021-6/+14
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| * Add testEddie Hung2019-07-022-0/+14
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* | Merge pull request #1147 from YosysHQ/clifford/fix1144Clifford Wolf2019-07-033-82/+26
|\ \ | | | | | | Improve specify dummy parser
| * | Fix tests/various/specify.vClifford Wolf2019-07-032-8/+3
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Some cleanups in "ignore specify parser"Clifford Wolf2019-07-032-80/+6
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Comment out invalid syntaxEddie Hung2019-06-301-2/+2
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| * | Add test from #1144, and try reading without '-specify' flagEddie Hung2019-06-282-0/+16
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| * | Improve specify dummy parser, fixes #1144Clifford Wolf2019-06-281-2/+9
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge pull request #1154 from whitequark/manual-sync-alwaysClifford Wolf2019-07-031-2/+3
|\ \ \ | | | | | | | | manual: explain the purpose of `sync always`
| * | | manual: explain the purpose of `sync always`.whitequark2019-07-021-2/+3
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* | | Merge pull request #1150 from YosysHQ/eddie/script_from_wireEddie Hung2019-07-023-8/+60
|\ \ \ | |/ / |/| | Add "script -select [selection]" to allow commands to be taken from wires
| * | Update test for Pass::call_on_module()Eddie Hung2019-07-021-1/+1
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| * | Use Pass::call_on_module() as per @cliffordwolf commentsEddie Hung2019-07-021-1/+1
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| * | Update test tooEddie Hung2019-07-021-2/+2
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| * | script -select -> script -scriptwireEddie Hung2019-07-022-6/+6
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| * | SpaceEddie Hung2019-07-011-0/+1
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| * | Move CHANGELOG entry from yosys-0.8 to 0.9Eddie Hung2019-07-011-7/+1
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| * | Merge branch 'master' into eddie/script_from_wireEddie Hung2019-07-014-5/+15
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| * \ \ Merge branch 'master' into eddie/script_from_wireEddie Hung2019-06-281-1/+1
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| * | | | Try command in another moduleEddie Hung2019-06-281-0/+3
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| * | | | Add to CHANGELOGEddie Hung2019-06-281-0/+6
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| * | | | Support ability for "script -select" to take commands from wiresEddie Hung2019-06-281-8/+39
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| * | | | Add testEddie Hung2019-06-281-0/+17
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* | | | | Merge pull request #1153 from YosysHQ/dave/fix_multi_muxDavid Shah2019-07-023-3/+25
|\ \ \ \ \ | | | | | | | | | | | | memory_dff: Fix checking of feedback mux input when more than one mux
| * | | | | memory_dff: Fix checking of feedback mux input when more than one muxDavid Shah2019-07-023-3/+25
|/ / / / / | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | / / Fix read_verilog assert/assume/etc on default case label, fixes ↵Clifford Wolf2019-07-021-0/+2
| |_|/ / |/| | | | | | | | | | | | | | | | | | | YosysHQ/SymbiYosys#53 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Move abc9 from yosys-0.8 to yosys-0.9 in CHANGELOGEddie Hung2019-07-011-5/+11
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* | | | Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2019-07-013-0/+4
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| * | | install *_nowide.lut filesEddie Hung2019-06-292-0/+3
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| * | | Merge pull request #1149 from gsomlo/gls-1098-abcext-fixupEddie Hung2019-06-281-0/+1
| |\ \ \ | | |/ / | |/| | Make abc9 pass aware of optional ABCEXTERNAL override
| | * | Make abc9 pass aware of optional ABCEXTERNAL overrideGabriel L. Somlo2019-06-281-0/+1
| | | | | | | | | | | | | | | | Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
* | | | autotest.sh to define _AUTOTB when test_autotbEddie Hung2019-06-281-1/+1
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* | | Replace log_assert() with meaningful log_error()Eddie Hung2019-06-281-1/+5
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* | | Remove peepopt call in synth_xilinx since already in synth -run coarseEddie Hung2019-06-281-5/+0
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* | Add missing CHANGELOG entriesEddie Hung2019-06-281-0/+3
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* | Fix spacingEddie Hung2019-06-281-2/+2
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* | Merge pull request #1098 from YosysHQ/xaigEddie Hung2019-06-2845-247/+3642
|\ \ | | | | | | "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
| * | Add generic __builtin_bswap32 functionEddie Hung2019-06-281-0/+15
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| * | Also fix write_aiger for UBEddie Hung2019-06-281-26/+26
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| * | Fix more potential for undefined behaviour due to container invalidationEddie Hung2019-06-281-6/+10
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| * | Update synth_ice40 -device doc to be relevant for -abc9 onlyEddie Hung2019-06-281-2/+2
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| * | Disable boxing of ECP5 dist RAM due to regressionEddie Hung2019-06-281-1/+1
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| * | Add write address to abc_scc_break of ECP5 dist RAMEddie Hung2019-06-281-1/+1
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| * | Fix DO4 typoEddie Hung2019-06-281-1/+1
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| * | Reduce diff with upstreamEddie Hung2019-06-271-4/+2
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| * | Extraneous newlineEddie Hung2019-06-271-1/+0
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