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verilog: impose limit on maximum expression width
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Designs with unreasonably wide expressions would previously get stuck
allocating memory forever.
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- Fix explicit size cast of unbased unsized literals
- Fix unbased unsized literal bound directly to port
- Output `is_unsized` flag in `dumpAst`
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Fixes #2639.
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cxxrtl: follow aliases to outlines when emitting $memrd.ADDR
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cxxrtl: add pass debug flag to show assigned wire types
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Refs #2543.
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cxxrtl: don't crash on empty designs
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verilog: fix sizing of ports with int types in module headers
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Declaring the ports as standard module items already worked as expected.
This adds a missing usage of `checkRange()` so that headers such as
`module m(output integer x);` now work correctly.
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- track depth so we know whether to consider higher-level elsifs
- error on unmatched endif/elsif/else
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New test cases on one branch may be automatically copied from simple/ to
simple_abc9/, causing failures when switching to another branch. This
updates the simple_abc9 script to set aside extraneous tests in a
non-destructive way.
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Add -nosynthesis flag for read_verilog command
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Add boost-python3
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If enable python-api, do need boost-python3.
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RTLIL Documentation: switch in process is optional
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genrtlil: improve name conflict error messaging
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sv: extended support for integer types
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- Standard data declarations can now use any integer type
- Parameters and localparams can now use any integer type
- Function returns types can now use any integer type
- Fix `parameter logic`, `localparam reg`, etc. to be 1 bit (previously 32 bits)
- Added longint type (64 bits)
- Unified parser source for integer type widths
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Fix digit-formatting calculation for small numbers.
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Signed-off-by: Henner Zeller <h.zeller@acm.org>
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Calling log10() on zero causes a non-sensical value to be calculated. On some
compile options, I've observed yosys crashing with an illegal
instruction (SIGILL).
To make it safe, fix the calculation to do a range check; wrap it a
decimal_digits() function, and use it where the previous ceil(log10(n)) call
was used. As a side, it also improves readability.
Signed-off-by: Henner Zeller <h.zeller@acm.org>
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Basically:
- priority converts to (* full_case *)
- unique0 converts to (* parallel_case *)
- unique converts to (* parallel_case, full_case *)
Fixes #2596.
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turn-off (#2566)
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Fix double-free on unmatched logger error pattern
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When an expected logger error pattern is unmatched, the logger raises
another (hidden) error. Because of the previous ordering of actions,
`logv_error_with_prefix()` would inadvertently invoke `yosys_atexit()`
twice, causing a double-free.
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Fixes #2600.
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verilog: fix sizing of constant args for tasks/functions
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- Simplify synthetic localparams for normal calls to update their width
- This step was inadvertently removed alongside `added_mod_children`
- Support redeclaration of constant function arguments
- `eval_const_function` never correctly handled this, but the issue
was not exposed in the existing tests until the recent change to
always attempt constant function evaluation when all-const args
are used
- Check asserts in const_arg_loop and const_func tests
- Add coverage for width mismatch error cases
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