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* Fitting help messages to 80 character widthKrystalDelusion2022-08-241-2/+2
| | | | | | | | | Uses the regex below to search (using vscode): ^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\); Finds any log messages double indented (which help messages are) and checks if *either* there are is no newline character at the end, *or* the number of characters before the newline is more than 80.
* Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}.Marcelina Kościelnicka2022-06-021-4/+15
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* memory_dff: Add support for no_rw_check attribute.Marcelina Kościelnicka2022-06-021-0/+10
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* FfData: some refactoring.Marcelina Kościelnicka2021-10-071-1/+1
| | | | | | | | | | - FfData now keeps track of the module and underlying cell, if any (so calling emit on FfData created from a cell will replace the existing cell) - FfData implementation is split off to its own .cc file for faster compilation - the "flip FF data sense by inserting inverters in front and after" functionality that zinit uses is moved onto FfData class and beefed up to have dffsr support, to support more use cases
* kernel/ff: Refactor FfData to enable FFs with async load.Marcelina Kościelnicka2021-10-021-7/+15
| | | | | | | | | | - *_en is split into *_ce (clock enable) and *_aload (async load aka latch gate enable), so both can be present at once - has_d is removed - has_gclk is added (to have a clear marker for $ff) - d_is_const and val_d leftovers are removed - async2sync, clk2fflogic, opt_dff are updated to operate correctly on FFs with async load
* memory_dff: Recognize soft transparency logic.Marcelina Kościelnicka2021-08-131-7/+451
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* memory_dff: Recognize read ports with reset / initial value.Marcelina Kościelnicka2021-08-111-7/+0
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* kernel/mem: Introduce transparency masks.Marcelina Kościelnicka2021-08-111-1/+2
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* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* Add new helper class for merging FFs into cells, use for memory_dff.Marcelina Kościelnicka2021-05-231-237/+104
| | | | Fixes #1854.
* memory_dff: Use Mem helper.Marcelina Kościelnicka2021-05-211-19/+26
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* memory_dff: Remove now-useless write port handling.Marcelina Kościelnicka2021-03-081-71/+7
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* memory_dff: Remove code looking for $mux cells.Marcelina Kościelnicka2021-03-081-56/+12
| | | | This job is now performed by `opt_dff`, which runs before this pass.
* memory_dff: Fix needlessly duplicating enable bits.Marcelina Kościelnicka2020-10-221-0/+8
| | | | | | | | | When the register being merged into the EN signal happens to be a $sdff, the current code creates a new $mux for every bit, even if they happen to be identical (as is usually the case), preventing proper grouping further down the flow. Fix this by adding a simple cache. Fixes #2409.
* memory_dff: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-12/+5
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* memory_dff: recognize more dff cellsMarcelina Kościelnicka2020-07-231-11/+112
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* Use C++11 final/override keywords.whitequark2020-06-181-2/+2
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* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-46/+46
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* kernel: use more ID::*Eddie Hung2020-04-021-8/+8
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* Make liberal use of IdString.in()Eddie Hung2019-08-061-1/+1
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* memory_dff: Fix checking of feedback mux input when more than one muxDavid Shah2019-07-021-3/+5
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Fix spacingEddie Hung2019-06-251-4/+3
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* Move only one consumer check outside of while loopEddie Hung2019-06-251-6/+5
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* Walk through as many muxes as exist for rd_enEddie Hung2019-06-241-8/+16
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* memory_dff: Fix typo when checking init valueDavid Shah2018-12-181-1/+1
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
| | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* Disable memory_dff for initialized FFsClifford Wolf2018-05-281-1/+19
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
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* Fixed some visual studio warningsClifford Wolf2016-02-131-1/+1
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* Bugfix in memory_dffClifford Wolf2015-10-311-1/+12
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* Added read-enable to memory modelClifford Wolf2015-09-251-9/+43
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* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
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* Modernized memory_dff (and fixed a bug)Clifford Wolf2015-06-141-147/+164
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* Merge clock inverters in memory_dffClifford Wolf2015-06-091-16/+37
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* namespace YosysClifford Wolf2014-09-271-6/+10
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* Fixed $memwr/$memrd order in memory_dffClifford Wolf2014-09-161-4/+6
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* Various improvements in memory_dff passClifford Wolf2014-08-061-21/+22
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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-19/+19
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* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-311-1/+1
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* Using log_assert() instead of assert()Clifford Wolf2014-07-281-1/+0
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* Using new obj iterator API in a few placesClifford Wolf2014-07-271-15/+11
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* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
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* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-3/+3
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* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-261-7/+2
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* Manual fixes for new cell connections APIClifford Wolf2014-07-261-4/+7
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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-19/+19
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-19/+19
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* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-231-1/+0
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* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-231-8/+4
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* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵Clifford Wolf2014-07-221-1/+1
| | | | created interim RTLIL::SigSpec::chunks_rw()
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