| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | intel: Map M9K BRAM only on families that have it | Dan Ravensloft | 2019-07-23 | 1 | -33/+0 |
| | | | | | | | | | This regresses Cyclone V and Cyclone 10 substantially, but these numbers were artificial, targeting a BRAM that they did not contain. Amusingly, synth_intel still does better when synthesizing PicoSoC than Quartus when neither are inferring block RAM. | ||||
| * | Clean whitespace and permissions in techlibs/intel | Larry Doolittle | 2017-10-05 | 1 | -0/+0 |
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| * | Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ↵ | dh73 | 2017-10-01 | 1 | -0/+33 |
| M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now | |||||
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index : iCE40/yosys | |
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