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* Remove extra newlineEddie Hung2019-06-031-1/+0
* Execute techmap and arith_map simultaneouslyEddie Hung2019-06-031-6/+6
* Add "stat -tech xilinx"Clifford Wolf2019-05-111-1/+1
* Add "synth_xilinx -arch"Clifford Wolf2019-05-071-1/+13
* Back to passing all xc7srl tests!Eddie Hung2019-05-011-5/+4
* Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fineEddie Hung2019-05-011-165/+97
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| * Refactor synth_xilinx to auto-generate docEddie Hung2019-04-261-153/+95
* | WIPEddie Hung2019-04-281-36/+22
* | Revert synth_xilinx 'fine' label more to how it used to be...Eddie Hung2019-04-261-21/+40
* | Where did this check come from!?!Eddie Hung2019-04-261-1/+0
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* Update help messageEddie Hung2019-04-221-1/+1
* Move 'shregmap -tech xilinx' into map_cellsEddie Hung2019-04-221-17/+20
* Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-04-221-0/+2
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| * Re-added clean after techmap in synth_xilinxClifford Wolf2019-04-221-0/+2
* | Tidy up, fix for -nosrlEddie Hung2019-04-211-8/+7
* | Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-211-2/+2
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| * Merge branch 'master' into map_cells_before_map_lutsEddie Hung2019-04-211-11/+12
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| | * Revert "synth_* with -retime option now calls abc with -D 1 as well"Eddie Hung2019-04-181-2/+2
| | * synth_* with -retime option now calls abc with -D 1 as wellEddie Hung2019-04-101-2/+2
* | | Add commentsEddie Hung2019-04-211-0/+7
* | | Use new pmux2shiftx from #944, remove my old attemptEddie Hung2019-04-211-3/+8
* | | Call shregmap twice -- once for variable, another for fixedEddie Hung2019-04-051-8/+11
* | | Move dffinit til after abcEddie Hung2019-04-051-2/+2
* | | Merge branch 'eddie/fix_retime' into xc7srlEddie Hung2019-04-051-7/+8
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| * | Move techamp t:$_DFF_?N? to before abc callEddie Hung2019-04-051-2/+2
| * | Resolve @daveshah1 comment, update synth_xilinx helpEddie Hung2019-04-051-3/+5
| * | synth_xilinx to techmap FFs after abc call, otherwise -retime failsEddie Hung2019-04-051-3/+3
* | | techmap inside map_cells stageEddie Hung2019-04-051-1/+1
* | | Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-041-0/+1
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| * | Missing techmap entry in helpEddie Hung2019-04-041-0/+1
* | | Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-041-12/+12
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| * | synth_xilinx to map_cells before map_lutsEddie Hung2019-04-041-12/+12
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* | t:$dff* -> t:$dff t:$dffeEddie Hung2019-04-041-2/+2
* | -nosrl meant when -nobramEddie Hung2019-04-031-1/+1
* | Disable shregmap in synth_xilinx if -retimeEddie Hung2019-04-031-3/+3
* | synth_xilinx to use shregmap with -minlen 3Eddie Hung2019-03-251-2/+2
* | Add '-nosrl' option to synth_xilinxEddie Hung2019-03-211-6/+16
* | Restore original synth_xilinx commandsEddie Hung2019-03-191-1/+2
* | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-191-2/+4
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| * Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873Clifford Wolf2019-03-191-2/+4
* | Cleanup synth_xilinxEddie Hung2019-03-151-2/+1
* | WorkingEddie Hung2019-03-151-7/+9
* | MisspellEddie Hung2019-03-141-1/+1
* | Revert "Add shregmap -init_msb_first and use in synth_xilinx"Eddie Hung2019-03-141-3/+2
* | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-141-16/+54
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| * Merge pull request #842 from litghost/merge_upstreamClifford Wolf2019-03-051-16/+52
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| | * Use singular for disabling of DRAM or BRAM inference.Keith Rothman2019-03-011-13/+13
| | * Modify arguments to match existing style.Keith Rothman2019-03-011-6/+6
| | * Changes required for VPR place and route synth_xilinx.Keith Rothman2019-03-011-16/+52
| * | Use "write_edif -pvector bra" for Xilinx EDIF filesClifford Wolf2019-03-051-1/+1
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