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| | * Add a xilinx_finalise passEddie Hung2019-09-231-0/+2
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| | * Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40Eddie Hung2019-09-201-1/+1
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| | * Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dspEddie Hung2019-09-191-1/+3
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| | * | synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2Eddie Hung2019-09-191-1/+4
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| | * | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-181-6/+15
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| | * | | Missing spaceEddie Hung2019-09-111-0/+1
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| | * | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-111-10/+13
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| | * | | | Move "(skip if -nodsp)" message to labelEddie Hung2019-09-101-4/+4
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| | * | | | Really get rid of 'opt_expr -fine' by being explicitEddie Hung2019-09-101-3/+0
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| | * | | | Remove wreduce callEddie Hung2019-09-101-1/+0
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| | * | | | Add comment for why opt_expr is necessaryEddie Hung2019-09-101-0/+2
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| | * | | | Revert "Remove "opt_expr -fine" call"Eddie Hung2019-09-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit bfda921d0317bfb4cb6fc9de8a556c2258b709bc.
| | * | | | Rename label to map_dspEddie Hung2019-09-101-1/+1
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| | * | | | Remove "opt_expr -fine" callEddie Hung2019-09-101-1/+0
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| | * | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-051-9/+12
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| | * \ \ \ \ Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-301-14/+23
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| | * \ \ \ \ \ Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-08-301-1/+52
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| | | * \ \ \ \ \ Merge branch 'master' into xc7dspDavid Shah2019-08-301-13/+68
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| | * | \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-201-14/+17
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| | * \ \ \ \ \ \ \ \ Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-08-151-1/+5
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| | | * | | | | | | | xilinx: Rework labels for faster Verilator testingDavid Shah2019-08-131-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | | | | | | | | Add DSP_A_MAXWIDTH_PARTIAL, refactorEddie Hung2019-08-131-1/+1
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| | * | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-121-1/+1
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| | * | | | | | | | | Pack partial-product adder DSP48E1 packingEddie Hung2019-08-091-0/+2
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| | * | | | | | | | | Combine techmap callsEddie Hung2019-08-081-2/+1
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| | * | | | | | | | | Move xilinx_dsp to before alumaccEddie Hung2019-08-081-6/+4
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| | * | | | | | | | | Change $__softmul back to $mulEddie Hung2019-08-011-0/+1
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| | * | | | | | | | | Use single DSP_SIGNEDONLY macroEddie Hung2019-07-181-1/+1
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| | * | | | | | | | | Update commentEddie Hung2019-07-171-5/+3
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| | * | | | | | | | | Revert drop down to 24x16 multipliers for allEddie Hung2019-07-161-1/+1
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| | * | | | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-161-1/+5
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| | | * | | | | | | | | xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 ↵David Shah2019-07-161-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | signed) Signed-off-by: David Shah <dave@ds0.me>
| | * | | | | | | | | | Oops forgot these filesEddie Hung2019-07-151-0/+4
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| | * | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-151-5/+20
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| | * | | | | | | | | | Move dsp_map.v into cells_map.v; cleanup synth_xilinx a littleEddie Hung2019-07-101-4/+1
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| | * | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-101-43/+58
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| | * | | | | | | | | | | xc7: Map combinational DSP48E1sDavid Shah2019-07-081-5/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | | | | | | Big rework; flop info now mostly in cells_sim.vEddie Hung2019-09-281-2/+2
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* | | | | | | | | | | / Missing an '&'Eddie Hung2019-09-261-1/+1
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* | | | | | | | | | | Use extractinv for synth_xilinx -iseMarcin Kościelnicki2019-09-191-1/+3
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* | | | | | | | | | xilinx: Make blackbox library family-dependent.Marcin Kościelnicki2019-09-151-6/+15
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* | | | | | | | | synth_xilinx: Support init values on Spartan 6 flip-flops properly.Marcin Kościelnicki2019-09-071-10/+13
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* | | | | | | | Merge branch 'eddie/xilinx_srl' into xaig_arrivalEddie Hung2019-08-281-15/+22
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| * | | | | | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srlEddie Hung2019-08-281-1/+45
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| * | | | | | | Merge branch 'master' into eddie/xilinx_srlEddie Hung2019-08-261-0/+8
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| * | | | | | | | xilinx_srl now copes with word-level flops $dff{,e}Eddie Hung2019-08-231-8/+3
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| * | | | | | | | Add variable length support to xilinx_srlEddie Hung2019-08-211-4/+3
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| * | | | | | | | abc9 to perform new 'map_ffs' before 'map_luts'Eddie Hung2019-08-211-3/+18
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| * | | | | | | | Add init supportEddie Hung2019-08-211-1/+1
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* | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-281-1/+53
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