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* | | TypoEddie Hung2019-06-031-1/+1
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* | | IS_C_INVERTEDEddie Hung2019-06-031-4/+4
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* | | Fix `ifndefEddie Hung2019-06-031-1/+1
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* | | Add flops as blackboxesEddie Hung2019-05-312-0/+27
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* | | Add FD*E_1 -> FD*E techmap rulesEddie Hung2019-05-311-5/+31
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* | | Techmap flops before ABC againEddie Hung2019-05-311-4/+4
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* | | Merge branch 'xaig' into xc7muxEddie Hung2019-05-311-0/+1
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| * \ \ Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-226-36/+222
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| * \ \ \ Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-221-8/+10
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| * \ \ \ \ Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-202-10/+12
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* | | | | | | Remove whitebox attribute from DRAMs for nowEddie Hung2019-05-301-2/+2
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* | | | | | | Carry in/out to be the last input/output for chains to be preservedEddie Hung2019-05-302-12/+15
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* | | | | | | Some more realistic delays...Eddie Hung2019-05-291-7/+7
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* | | | | | | TypoEddie Hung2019-05-281-1/+1
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* | | | | | | Make MUXF{7,8} and CARRY4 whiteboxEddie Hung2019-05-271-3/+3
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* | | | | | | Re-enable lib_whiteboxEddie Hung2019-05-271-5/+5
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* | | | | | | BlackboxesEddie Hung2019-05-262-10/+10
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* | | | | | | Muck about with LUT delays some moreEddie Hung2019-05-261-5/+5
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* | | | | | | Try new LUT delaysEddie Hung2019-05-241-8/+11
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* | | | | | | Transpose CARRY4 delaysEddie Hung2019-05-241-10/+8
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* | | | | | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-05-231-0/+4
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| * | | | | | Add "min bits" and "min wports" to xilinx dram rulesEddie Hung2019-05-231-0/+4
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* | | | | | | Add whitebox support to DRAMEddie Hung2019-05-235-24/+26
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* | | | | | | shift register inference before muxEddie Hung2019-05-221-3/+3
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* | | | | | | Fix/workaround symptom unveiled by #1023Eddie Hung2019-05-211-4/+14
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* | | | | | | Instead of MUXCY/XORCY use CARRY4 (with timing)Eddie Hung2019-05-214-11/+20
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* | | | | | | Modify LUT area cost to be same as old abcEddie Hung2019-05-211-10/+9
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* | | | | | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-05-212-8/+23
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| * | | | | | Add "stat -tech xilinx"Clifford Wolf2019-05-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | Add "synth_xilinx -arch"Clifford Wolf2019-05-071-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | Rename cells_map.v to prevent clash with ff_map.vEddie Hung2019-05-031-6/+8
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* | | | | | | Trim off leading 1'bx in AEddie Hung2019-05-021-7/+20
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* | | | | | | Add don't care optimisationEddie Hung2019-05-021-0/+11
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* | | | | | | Use new peepopt from #969Eddie Hung2019-05-021-10/+15
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* | | | | | | Revert to pre-muxcover approachEddie Hung2019-05-022-25/+82
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* | | | | | | Missing help_modeEddie Hung2019-05-021-1/+1
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* | | | | | | Fix -nocarryEddie Hung2019-05-021-3/+3
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* | | | | | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-05-023-176/+116
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| * | | | | | Back to passing all xc7srl tests!Eddie Hung2019-05-011-5/+4
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| * | | | | | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fineEddie Hung2019-05-011-165/+97
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| | * | | | | | Refactor synth_xilinx to auto-generate docEddie Hung2019-04-261-153/+95
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| * | | | | | WIPEddie Hung2019-04-281-36/+22
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| * | | | | | Move neg-pol to pos-pol mapping from ff_map to cells_map.vEddie Hung2019-04-282-9/+12
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| * | | | | | Revert synth_xilinx 'fine' label more to how it used to be...Eddie Hung2019-04-261-21/+40
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* | | | | | Fix spacingEddie Hung2019-04-261-4/+4
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* | | | | | Apparently, this reduces number of MUXCY/XORCYEddie Hung2019-04-261-10/+9
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* | | | | | Try a different approach with 'muxcover'Eddie Hung2019-04-262-88/+36
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* | | | | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-04-261-1/+0
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| * | | | | Where did this check come from!?!Eddie Hung2019-04-261-1/+0
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* | | | | Remove split_shiftx callEddie Hung2019-04-261-4/+1
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