aboutsummaryrefslogtreecommitdiffstats
path: root/chipset_enable.c
Commit message (Expand)AuthorAgeFilesLines
* chipset_enable.c: Spell `BIOS` in uppercaseAngel Pons2020-05-031-1/+1
* chipset_enable.c: Disable SPI on ICH7 if booted from LPCAngel Pons2020-04-171-0/+8
* chipset_enable.c: Add more Lewisburg PCH IDsAngel Pons2020-03-271-0/+8
* chipset_enable: Mark Intel HM75 as DEPEvgeny Zinoviev2020-03-191-1/+1
* chipset_enable.c: Mark Skylake U Premium as DEPAngel Pons2020-03-191-1/+1
* chipset_enable.c: Add Ice Lake U to known and tested systemsJohanna Schander2020-02-091-0/+1
* chipset_enable: Add Kaby Lake U Prem. to known and tested systemsWim Vervoorn2020-01-221-1/+1
* chipset_enable.c: Mark Intel HM76 as DEPAngel Pons2019-12-211-1/+1
* chipset_enable.c: Mark Intel Q75 as DEPAngel Pons2019-10-081-1/+1
* chipset_enable: Mark Intel CM236 and CM246 as DEPNico Huber2019-08-081-2/+2
* chipset_enable: Add support for Cannon Lake U PremiumMatt DeVillier2019-08-081-0/+1
* ichspi: Add support for discrete Cannon Lake PCHsNico Huber2019-08-081-10/+10
* chipset_enable: Add support for discrete Cannon Lake PCHsThomas Heijligen2019-08-081-0/+18
* chipset_enable: Fix recent -Wmissing-field-initializer troubleNico Huber2019-07-311-14/+14
* ichspi: Add Apollo Lake supportNico Huber2019-07-061-1/+1
* chipset_enable: Add Apollo LakeNico Huber2019-07-061-4/+20
* Rework internal bus handling and laptop bail-outNico Huber2019-06-061-377/+440
* chipset_enable: Mark Intel QS77 as DEPEvgeny Zinoviev2019-06-031-1/+1
* Remove trailing whitespaceElyes HAOUAS2019-03-041-1/+1
* chipset_enable.c: Mark Intel C224 as DEPTristan Corrick2018-12-221-1/+1
* chipset_enable.c: Mark Intel PM55 as DEPAngel Pons2018-11-031-1/+1
* chipset_enable.c: Mark Intel H81 as DEPTristan Corrick2018-11-011-1/+1
* chipset_enable.c: Mark Intel HM65 as DEPAngel Pons2018-10-081-1/+1
* Remove unneeded whitespaceElyes HAOUAS2018-10-051-1/+1
* chipset_enable.c: Mark Broadwell U Premium as DEPAngel Pons2018-10-031-1/+1
* chipset_enable.c: Mark Intel HM55 as DEPAngel Pons2018-08-221-1/+1
* Remove unneeded white spacesElyes HAOUAS2018-06-241-2/+2
* chipset_enable: Add PCI IDs for discrete Kaby Lake PCHsNico Huber2018-06-041-0/+7
* Remove address from GPLv2 headersElyes HAOUAS2018-04-241-4/+0
* Fix whitespace errorsElyes HAOUAS2018-04-241-1/+1
* chipset_enable: Mark VX855 as testedLubomir Rintel2018-01-261-1/+1
* chipset_enable: Mark VX900 as testedLubomir Rintel2018-01-021-1/+1
* vt_vx: check whether the chipset's MMIO range is configuredLubomir Rintel2018-01-021-0/+8
* chipset_enable: Mark SiS 630 as tested OKNico Huber2017-11-211-1/+1
* sb600spi: Add support for Merlin Falcon ChipsetRicardo Ribalda Delgado2017-09-171-0/+1
* chipset_enable: Add support for C620-series Lewisburg PCHDavid Hendricks2017-09-011-2/+27
* chipset_enable: Mark Braswell as testedDavid Hendricks2017-08-191-1/+1
* rpci: Use pci_dev struct pointer to avoid API breaksYouness Alaoui2017-08-101-0/+5
* chipset_enable: Set 100 series chipsets to NTNico Huber2017-07-281-30/+30
* chipset_enable: Add support for Intel Skylake / KabylakeNico Huber2017-07-281-7/+110
* ichspi: Drop `dev` parameter from init functionsNico Huber2017-06-201-4/+4
* Handle Intel Wildcat Point *LP* like Lynx Point LPNico Huber2017-06-201-8/+16
* Move register decodes into enable_flash_ich_handle_gcs()Nico Huber2017-04-251-4/+18
* Add a bunch of new/tested stuff and various small changes 24Stefan Tauner2016-01-231-3/+10
* Add support for VIA VT8251Stefan Tauner2015-11-211-0/+1
* Add a bunch of new/tested stuff and various small changes 22Stefan Tauner2015-02-081-36/+42
* Add support for Intel Wildcat Point PCHDuncan Laurie2014-08-201-2/+17
* Add support for Intel Silvermont: Bay Trail, Rangeley and AvotonDuncan Laurie2014-08-201-53/+176
* Add a bunch of new/tested stuff and various small changes 21Stefan Tauner2014-08-061-1/+1
* Refine messages regarding AMD FCH flash protectionsStefan Tauner2014-07-151-5/+8
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-04 21:53:34 +0000