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* testsuite: add reproducer for #76Tristan Gingold2019-12-312-0/+38
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* Add more tests for issue#36Tristan Gingold2019-12-053-0/+71
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* Add testcase for #73Tristan Gingold2019-12-054-0/+63
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* handle mem_rd_sync gates.Tristan Gingold2019-12-051-0/+10
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* Handle removal of id_output gates.Tristan Gingold2019-12-051-28/+10
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* Fix init input for iadff. For #76Tristan Gingold2019-12-031-1/+1
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* Add test for #75Tristan Gingold2019-12-032-0/+55
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* Do not rename ports. Fix #75Tristan Gingold2019-12-031-8/+9
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* Support multiple synthesis. Fix #73Tristan Gingold2019-12-021-4/+7
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* Adjust pr61 testcase to avoid constant propagation.Tristan Gingold2019-11-161-2/+6
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* Add testcase from #36Tristan Gingold2019-11-072-0/+42
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* Add testcase for #65Tristan Gingold2019-11-074-0/+31
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* Add testcase from issue 1001Tristan Gingold2019-11-063-0/+82
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* testsuite: reduce verbosity.Tristan Gingold2019-11-063-4/+4
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* testsuite: add xfail1 testTristan Gingold2019-11-054-0/+37
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* testsuite: add case for issue 999Tristan Gingold2019-11-052-0/+43
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* testsuite.sh: simplify (only sub sub dirs).Tristan Gingold2019-11-051-21/+3
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* testsuite: move pr tests in issues/Tristan Gingold2019-11-0510-17/+28
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* testsuite: move tests of examples in a subdir.Tristan Gingold2019-11-057-43/+43
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* testsuite: add issue1000Tristan Gingold2019-11-052-0/+51
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* testsuite: add synth_ice40 (from synth), add synth_import.Tristan Gingold2019-11-051-2/+14
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* testenv: use abs_topdir for default ghdl.so path.Tristan Gingold2019-11-051-1/+8
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* Add testcase for #68Tristan Gingold2019-11-042-0/+31
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* testsuite: it is now possible to run a single test.Tristan Gingold2019-11-0414-11/+32
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* Add Id_Smod support (#66)Anton Blanchard2019-11-033-0/+27
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* add iadff (#67)Pepijn de Vos2019-11-031-1/+8
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* rewrite import_memory, directly generate $memTristan Gingold2019-11-031-97/+130
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* handle formal input ports.Tristan Gingold2019-10-311-5/+31
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* Handle Id_Cover_AssertTristan Gingold2019-10-221-0/+2
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* Initial support of memories.Tristan Gingold2019-10-191-18/+152
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* Sign extend 32b literals (#61)Pepijn de Vos2019-10-163-4/+78
| | | | | | | | | | | | | | | | | | | * sign extend 32b literals * Fix undefined behavior Right shift of a signed values is undefined but does arithemetic shift in practice. However, shifting by more than one int width is also undefined but *wraps around*. This caused bit/log to work because it'd shift mod 32. But it actually cause the UL32 to be wrong because it'd just repeat the value rather than extending. * zero pad unsigned and add signed * add testsuite
* Add Id_Neg support (#63)Anton Blanchard2019-10-163-0/+27
| | | | | | | | * Add Id_Neg support * Add testcase for Id_Neg Thanks to Pepijn for the example I based this on.
* Add Id_Smul and Id_Umul (#64)Anton Blanchard2019-10-163-0/+34
| | | | | | * Add Id_Smul and Id_Umul support * Add testcase for Id_Smul and Id_Umul
* Fix a couple of compiler warnings (#62)Anton Blanchard2019-10-141-3/+3
| | | | | | | | | | | | | | | | | I see a few compiler warnings on gcc 9.2: src/ghdl.cc: In function ‘Yosys::RTLIL::SigSpec get_src(std::vector<Yosys::RTLIL::Wire*>&, GhdlSynth::Net)’: src/ghdl.cc:123:43: warning: ‘valzx’ may be used uninitialized in this function [-Wmaybe-uninitialized] 123 | switch(((val01 >> i)&1)+((valzx >> i)&1)*2) | ~~~~~~~^~~~~ src/ghdl.cc:123:26: warning: ‘val01’ may be used uninitialized in this function [-Wmaybe-uninitialized] 123 | switch(((val01 >> i)&1)+((valzx >> i)&1)*2) | ~~~~~~~^~~~~ src/ghdl.cc:99:26: warning: ‘val’ may be used uninitialized in this function [-Wmaybe-uninitialized] 99 | bits[i] = (val >> i) & 1 ? RTLIL::State::S1 : RTLIL::State::S0; | ~~~~~^~~~~ These both appear to be spurious, but initialize them to 0 to avoid the warning.
* Handle Id_Sextend (#59)T. Meissner2019-10-091-0/+8
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* testsuite: Add formal tests (#57)T. Meissner2019-10-0725-25/+359
| | | | | | | | | | | | | | | | | | * Add formal tests for shift operations * ci: build ghdl/synth:formal and run test suites in it * add testsuite/formal/testsuite.sh * create testsuite/issues * ci: remove a level of grouping * testenv: fix SYMBIYOSYS * refactor * testsuite/formal/shifts: Add check for shifts > vector length
* Handle Id_Asr (#55)T. Meissner2019-10-061-0/+4
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* add shift functions (#54)Pepijn de Vos2019-10-061-0/+8
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* Handle Const_X & Const_Z (#49)T. Meissner2019-10-051-0/+12
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* handle Const_LogTristan Gingold2019-10-021-25/+34
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* Handle Const_Bit.Tristan Gingold2019-10-021-0/+14
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* Handle covers (#43)T. Meissner2019-09-201-0/+4
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* Remove Id_Insert (unused).Tristan Gingold2019-09-091-17/+0
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* Fix incomplete handling of ConcatnTristan Gingold2019-09-071-2/+3
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* Icestick uart (#37)marph912019-08-227-0/+212
| | | | | | * added UART example for the icestick * extended testsuite by the UART example
* Run testsuite in Travis CI with docker images (#31)1138-4EB2019-08-1617-123/+275
| | | | | | | | | | | | * makefile: use '--build' shortcut to build ghdl.so * move: rename subdir 'ghdl' to 'src' * travis: add travis config file, build script and utils script * testsuite: do not call ghdl explicitly * readme: update
* handle utrunc/strunc. For #33Tristan Gingold2019-08-161-0/+10
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* Use libghdl to build the module. Update instructions.Tristan Gingold2019-08-152-23/+24
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* ghdl: initialize for synthesis.Tristan Gingold2019-08-141-2/+7
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* Build with libghdl (WIP).Tristan Gingold2019-08-142-2/+2
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