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simulate
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Author
Age
Files
Lines
*
vhdl: remove severity from cover, report and severity from assume.
Tristan Gingold
2019-08-08
1
-1
/
+1
*
Add support for PSL assumptions, used in formal verification (#880)
Pepijn de Vos
2019-08-07
2
-3
/
+11
*
simul-elaboration: rewrite assertion.
Tristan Gingold
2019-07-13
1
-3
/
+3
*
vhdl simul-elaboration: minor rewrite.
Tristan Gingold
2019-07-08
1
-3
/
+1
*
vhdl: rename Cover_Statement to Cover_Directive.
Tristan Gingold
2019-07-04
2
-4
/
+4
*
ghdl_jit: almost add ghdlsynth
Tristan Gingold
2019-06-29
2
-234
/
+0
*
vhdl: move annotations from simul to vhdl.
Tristan Gingold
2019-06-29
8
-1479
/
+6
*
synth: get rid of execution and elaboration.
Tristan Gingold
2019-06-19
2
-40
/
+56
*
vhdl: decouple annotations from environments.
Tristan Gingold
2019-06-19
8
-204
/
+190
*
vhdl/simulate: fix regression wrt package instances.
Tristan Gingold
2019-06-12
2
-4
/
+6
*
simul: refine scalar type annotations.
Tristan Gingold
2019-06-12
2
-17
/
+49
*
synth: handle integer +/- for constants.
Tristan Gingold
2019-06-08
2
-2
/
+4
*
grt: extract grt.to_strings from grt.images
Tristan Gingold
2019-06-01
1
-9
/
+10
*
vhdl: differenciate block and line comments.
Tristan Gingold
2019-05-30
2
-5
/
+5
*
vhdl/simulate: ignore some constructs for synthesis.
Tristan Gingold
2019-05-23
2
-3
/
+5
*
Add simple_IO - to be used instead of Text_IO.
Tristan Gingold
2019-05-19
7
-49
/
+42
*
vhdl: decouple errorouts a bit more.
Tristan Gingold
2019-05-10
1
-2
/
+2
*
psl: add psl-types, psl-nodes_priv.
Tristan Gingold
2019-05-10
1
-0
/
+1
*
vhdl: replace Iir_Int64 by Int64, and Iir_Fp64 by Fp64.
Tristan Gingold
2019-05-10
3
-8
/
+7
*
Extract psl-errors from errorout.
Tristan Gingold
2019-05-10
1
-1
/
+1
*
vhdl: extract vhdl.errors from errorout.
Tristan Gingold
2019-05-08
6
-3
/
+6
*
vhdl: renames iirs_walk to vhdl-nodes_walk
Tristan Gingold
2019-05-08
1
-1
/
+1
*
vhdl-nodes_utils: renaming.
Tristan Gingold
2019-05-07
1
-2
/
+2
*
vhdl: renames iir_chains to vhdl.nodes_utils. Remove iir_chain_handling.
Tristan Gingold
2019-05-06
2
-2
/
+2
*
vhdl: move iirs_utils to vhdl.utils
Tristan Gingold
2019-05-06
6
-6
/
+6
*
vhdl: rename iirs to vhdl.nodes
Tristan Gingold
2019-05-05
8
-8
/
+8
*
vhdl: move evaluation to vhdl child.
Tristan Gingold
2019-05-05
2
-8
/
+8
*
vhdl: move ieee packages to vhdl children.
Tristan Gingold
2019-05-05
1
-2
/
+2
*
vhdl: move std_standard package to vhdl child.
Tristan Gingold
2019-05-05
4
-11
/
+11
*
vhdl: move sem* packages to vhdl children.
Tristan Gingold
2019-05-05
3
-11
/
+11
*
vhdl: move canon to a vhdl child package.
Tristan Gingold
2019-05-05
1
-2
/
+2
*
vhdl: move disp_tree and disp_vhdl as vhdl child.
Tristan Gingold
2019-05-04
2
-5
/
+5
*
vhdl: move parse package as vhdl child.
Tristan Gingold
2019-05-04
1
-3
/
+4
*
vhdl: move tokens as vhdl child package.
Tristan Gingold
2019-05-04
1
-2
/
+2
*
vhdl: move scanner under vhdl hierarchy.
Tristan Gingold
2019-05-04
1
-5
/
+5
*
simul: do not reverse the list twice; renaming.
Tristan Gingold
2019-04-16
1
-24
/
+16
*
fix gnat8 errors for libghdlsynth targets
Stefan Biereigel
2019-03-13
2
-3
/
+0
*
simul: refactoring.
Tristan Gingold
2019-01-11
2
-25
/
+29
*
simul: handle PSL assert finalizer.
Tristan Gingold
2019-01-06
1
-4
/
+57
*
simul: handle array values. Reformating.
Tristan Gingold
2018-12-29
1
-83
/
+87
*
iir_kind_selected_element: use Named_Entity for homogeneity.
Tristan Gingold
2018-12-18
1
-2
/
+2
*
Extract grt.astdio.vhdl from grt.astdio.
Tristan Gingold
2018-12-16
2
-2
/
+3
*
files_map: renaming for consistency.
Tristan Gingold
2018-12-14
1
-2
/
+2
*
simul: adjust after previous changes.
Tristan Gingold
2018-11-15
1
-2
/
+3
*
Improve doc, fix English typo.
Tristan Gingold
2018-09-23
1
-5
/
+6
*
Add support for --time-resolution (jit only). Fix #613
Tristan Gingold
2018-08-10
1
-3
/
+1
*
simulate: remove use of Nam_Buffer.
Tristan Gingold
2018-01-20
1
-26
/
+30
*
simul: remove ports_map from instances (not used).
Tristan Gingold
2018-01-02
3
-9
/
+0
*
simul: adjust instance for conversion in calls.
Tristan Gingold
2017-12-21
1
-5
/
+5
*
simul: Add subprogram body in frames.
Tristan Gingold
2017-12-21
4
-36
/
+60
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