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| author | Keith Rothman <537074+litghost@users.noreply.github.com> | 2021-02-16 12:24:15 -0800 |
|---|---|---|
| committer | Keith Rothman <537074+litghost@users.noreply.github.com> | 2021-02-17 12:03:16 -0800 |
| commit | 5a7f83c705d6ea52e9e5bb7b182b32040d15a13a (patch) | |
| tree | 7e9d54dca77f867e76d034923dba95e1f52980ef /fpga_interchange/examples/lut | |
| parent | 7c1544f4d8e5dc75d6d6a8cf973888f5c94bd1b9 (diff) | |
| download | nextpnr-5a7f83c705d6ea52e9e5bb7b182b32040d15a13a.tar.gz nextpnr-5a7f83c705d6ea52e9e5bb7b182b32040d15a13a.tar.bz2 nextpnr-5a7f83c705d6ea52e9e5bb7b182b32040d15a13a.zip | |
Add examples invoking FPGA interchange nextpnr.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Diffstat (limited to 'fpga_interchange/examples/lut')
| -rw-r--r-- | fpga_interchange/examples/lut/Makefile | 8 | ||||
| -rw-r--r-- | fpga_interchange/examples/lut/lut.v | 5 | ||||
| -rw-r--r-- | fpga_interchange/examples/lut/lut.xdc | 5 | ||||
| -rw-r--r-- | fpga_interchange/examples/lut/run.tcl | 14 |
4 files changed, 32 insertions, 0 deletions
diff --git a/fpga_interchange/examples/lut/Makefile b/fpga_interchange/examples/lut/Makefile new file mode 100644 index 00000000..54fc8994 --- /dev/null +++ b/fpga_interchange/examples/lut/Makefile @@ -0,0 +1,8 @@ +DESIGN := lut +DESIGN_TOP := top +PACKAGE := csg324 + +include ../template.mk + +build/lut.json: lut.v | build + yosys -c run.tcl diff --git a/fpga_interchange/examples/lut/lut.v b/fpga_interchange/examples/lut/lut.v new file mode 100644 index 00000000..ca18e665 --- /dev/null +++ b/fpga_interchange/examples/lut/lut.v @@ -0,0 +1,5 @@ +module top(input i0, input i1, output o); + +assign o = i0 | i1; + +endmodule diff --git a/fpga_interchange/examples/lut/lut.xdc b/fpga_interchange/examples/lut/lut.xdc new file mode 100644 index 00000000..4f7e948b --- /dev/null +++ b/fpga_interchange/examples/lut/lut.xdc @@ -0,0 +1,5 @@ +set_property PACKAGE_PIN N16 [get_ports i0] +set_property PACKAGE_PIN N15 [get_ports i1] +set_property PACKAGE_PIN M17 [get_ports o] + +#set_property IOSTANDARD LVCMOS33 [get_ports] diff --git a/fpga_interchange/examples/lut/run.tcl b/fpga_interchange/examples/lut/run.tcl new file mode 100644 index 00000000..1edd8bb7 --- /dev/null +++ b/fpga_interchange/examples/lut/run.tcl @@ -0,0 +1,14 @@ +yosys -import + +read_verilog lut.v + +synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp + +# opt_expr -undriven makes sure all nets are driven, if only by the $undef +# net. +opt_expr -undriven +opt_clean + +setundef -zero -params + +write_json build/lut.json |