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Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify
Clifford Wolf
2019-05-06
3
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+32
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Merge pull request #988 from YosysHQ/clifford/fix987
Clifford Wolf
2019-05-04
2
-1
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+5
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Add approximate support for SV "var" keyword, fixes #987
Clifford Wolf
2019-05-04
2
-1
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+5
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Improve opt_clean handling of unused wires
Clifford Wolf
2019-05-04
1
-10
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+22
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Add support for SVA "final" keyword
Clifford Wolf
2019-05-04
2
-1
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+5
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Improve write_verilog specify support
Clifford Wolf
2019-05-04
3
-16
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+75
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Update README
Clifford Wolf
2019-05-04
1
-5
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+1
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More testing
Eddie Hung
2019-05-03
2
-2
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+5
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Fix spacing
Eddie Hung
2019-05-03
1
-6
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+6
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Add quick-and-dirty specify tests
Eddie Hung
2019-05-03
2
-0
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+53
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Merge remote-tracking branch 'origin/master' into clifford/specify
Eddie Hung
2019-05-03
40
-405
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+931
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Rename cells_map.v to prevent clash with ff_map.v
Eddie Hung
2019-05-03
1
-6
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+8
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iverilog with simcells.v as well
Eddie Hung
2019-05-03
1
-1
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+2
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Merge pull request #969 from YosysHQ/clifford/pmgenstuff
Clifford Wolf
2019-05-03
13
-151
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+509
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Update pmgen documentation
Clifford Wolf
2019-05-03
1
-6
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+18
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Fix typo
Clifford Wolf
2019-05-03
1
-1
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+1
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Add peepopt_muldiv, fixes #930
Clifford Wolf
2019-04-30
6
-1
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+86
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pmgen progress
Clifford Wolf
2019-04-30
4
-13
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+27
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Run "peepopt" in generic "synth" pass and "synth_ice40"
Clifford Wolf
2019-04-30
2
-0
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+4
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Some pmgen reorg, rename peepopt.pmg to peepopt_shiftmul.pmg
Clifford Wolf
2019-04-30
3
-4
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+6
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Progress in shiftmul peepopt pattern
Clifford Wolf
2019-04-30
1
-3
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+51
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Add "peepopt" skeleton
Clifford Wolf
2019-04-29
5
-1
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+112
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Add pmgen support for multiple patterns in one matcher
Clifford Wolf
2019-04-29
3
-130
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+188
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Support multiple pmg files (right now just concatenated together)
Clifford Wolf
2019-04-29
1
-6
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+30
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Merge pull request #984 from YosysHQ/eddie/fix_982
Clifford Wolf
2019-05-03
1
-1
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+2
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Revert "synth_xilinx to call dffinit with -noreinit"
Eddie Hung
2019-05-03
1
-1
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+1
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If init is 1'bx, do not add to dict as per @cliffordwolf
Eddie Hung
2019-05-03
1
-1
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+2
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Revert "dffinit -noreinit to silently continue when init value is 1'bx"
Eddie Hung
2019-05-03
1
-12
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+4
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synth_xilinx to call dffinit with -noreinit
Eddie Hung
2019-05-02
1
-1
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+1
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dffinit -noreinit to silently continue when init value is 1'bx
Eddie Hung
2019-05-02
1
-4
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+12
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Merge pull request #976 from YosysHQ/clifford/fix974
Clifford Wolf
2019-05-03
3
-0
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+25
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Add splitcmplxassign test case and silence splitcmplxassign warning
Clifford Wolf
2019-05-01
2
-0
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+23
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Fix width detection of memory access with bit slice, fixes #974
Clifford Wolf
2019-05-01
1
-0
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+2
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Merge pull request #985 from YosysHQ/clifford/fix981
Clifford Wolf
2019-05-03
2
-44
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+81
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Improve opt_expr and opt_clean handling of (partially) undriven and/or unused...
Clifford Wolf
2019-05-03
2
-44
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+81
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Fix typo in tests/svinterfaces/runone.sh
Clifford Wolf
2019-05-03
1
-2
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+2
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Merge pull request #979 from jakobwenzel/svinterfacesTestcase
Clifford Wolf
2019-05-03
1
-2
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+2
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fail svinterfaces testcases on yosys error exit
Jakob Wenzel
2019-05-02
1
-2
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+2
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Merge pull request #963 from YosysHQ/eddie/synth_xilinx_fine
Clifford Wolf
2019-05-02
3
-34
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+30
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Back to passing all xc7srl tests!
Eddie Hung
2019-05-01
1
-5
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+4
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Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fine
Eddie Hung
2019-05-01
22
-190
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+286
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WIP
Eddie Hung
2019-04-28
1
-36
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+22
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Move neg-pol to pos-pol mapping from ff_map to cells_map.v
Eddie Hung
2019-04-28
2
-9
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+12
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Revert synth_xilinx 'fine' label more to how it used to be...
Eddie Hung
2019-04-26
1
-21
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+40
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Merge pull request #978 from ucb-bar/fmtfirrtl
Eddie Hung
2019-05-01
1
-25
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+25
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Re-indent firrtl.cc:struct memory - no functional change.
Jim Lawson
2019-05-01
1
-25
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+25
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Merge branch 'master' of github.com:YosysHQ/yosys
Eddie Hung
2019-05-01
21
-176
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+273
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Merge branch 'clifford/fix883'
Clifford Wolf
2019-05-02
1
-0
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+1
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Add missing enable_undef to "sat -tempinduct-def", fixes #883
Clifford Wolf
2019-05-02
1
-0
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+1
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Merge pull request #977 from ucb-bar/fixfirrtlmem
Clifford Wolf
2019-05-01
3
-4
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+64
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