iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04	1	-0/+1
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*	More fixes for bugs found using xsthammer	Clifford Wolf	2013-06-13	1	-4/+2
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*	Sign-extension related fixes in SatGen and AST frontend	Clifford Wolf	2013-06-10	1	-0/+2
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*	Fixes and improvements in AST const folding	Clifford Wolf	2013-06-10	1	-1/+1
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*	Enabled AST/Verilog front-end optimizations per default	Clifford Wolf	2013-06-10	1	-3/+9
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*	Fixed a bug in AST frontend for cases with non-blocking assigned variables ↵	Clifford Wolf	2013-04-13	1	-4/+4
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*	Now only use value from "initial" when no matching "always" block is found	Clifford Wolf	2013-03-31	1	-5/+15
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*	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	Clifford Wolf	2013-03-31	1	-1/+3
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*	Fixed handling of unconditional generate blocks	Clifford Wolf	2013-03-26	1	-0/+1
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*	Added nosync attribute and some async reset related fixes	Clifford Wolf	2013-03-25	1	-3/+5
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*	Moved stand-alone libs to libs/ directory and added libs/subcircuit	Clifford Wolf	2013-02-27	1	-1/+1
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*	initial import	Clifford Wolf	2013-01-05	1	-0/+1054