| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | For case select values use Sa instead of Sx and Sz | Miodrag Milanovic | 2023-02-08 | 1 | -0/+1 |
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| * | Support importing verilog configurations using Verific | Miodrag Milanovic | 2022-11-25 | 1 | -1/+1 |
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| * | verific: Fix conditions of SVAs with explicit clocks within procedures | Jannis Harder | 2022-05-03 | 1 | -0/+1 |
| | | | | | | | | | | For SVAs that have an explicit clock and are contained in a procedure which conditionally executes the assertion, verific expresses this using a mux with one input connected to constant 1 and the other output connected to an SVA_AT. The existing code only handled the case where the first input is connected to 1. This patch also handles the other case. | ||||
| * | Import verific netlist in consistent order | Miodrag Milanovic | 2022-03-25 | 1 | -1/+1 |
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| * | Add support for $aldff flip-flops to verific importer | Claire Xenia Wolf | 2021-10-08 | 1 | -0/+1 |
| | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> | ||||
| * | Fixing old e-mail addresses and deadnames | Claire Xenia Wolf | 2021-06-08 | 1 | -1/+1 |
| | | | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g; | ||||
| * | verific: recover wiretype/enum attr as part of import_attributes() | Eddie Hung | 2020-04-27 | 1 | -1/+1 |
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| * | Do not rename VHDL entities to "entity(impl)" when they are top modules | Clifford Wolf | 2019-11-20 | 1 | -1/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Automatically prune init attributes in verific front-end, fixes #1237 | Clifford Wolf | 2019-08-07 | 1 | -2/+2 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Fix verific_parameters construction, use attribute to mark top netlists | Eddie Hung | 2019-05-03 | 1 | -1/+1 |
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| * | WIP -chparam support for hierarchy when verific | Eddie Hung | 2019-05-03 | 1 | -2/+2 |
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| * | Improve src tagging (using names and attrs) of cells and wires in verific ↵ | Clifford Wolf | 2018-12-18 | 1 | -0/+1 |
| | | | | | | | front-end Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add "verific -L <int>" option | Clifford Wolf | 2018-09-04 | 1 | -0/+2 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add automatic verific import in hierarchy command | Clifford Wolf | 2018-06-20 | 1 | -0/+3 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add (* gclk *) attribute support | Clifford Wolf | 2018-06-01 | 1 | -0/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Fix verific handling of anyconst/anyseq attributes | Clifford Wolf | 2018-05-24 | 1 | -1/+2 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add "verific -autocover" | Clifford Wolf | 2018-04-06 | 1 | -1/+2 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Fix handling of unclocked immediate assertions in Verific front-end | Clifford Wolf | 2018-03-26 | 1 | -1/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Fix Verific handling of "assert property (..);" in always block | Clifford Wolf | 2018-03-07 | 1 | -4/+6 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add "verific -import -V" | Clifford Wolf | 2018-03-07 | 1 | -2/+2 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add proper SVA seq.triggered support | Clifford Wolf | 2018-03-04 | 1 | -1/+11 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add VerificClocking class and refactor Verific DFF handling | Clifford Wolf | 2018-03-04 | 1 | -3/+14 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Fixes and improvements in Verific SVA importer | Clifford Wolf | 2018-03-01 | 1 | -1/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Continue refactoring of Verific SVA importer code | Clifford Wolf | 2018-02-28 | 1 | -6/+4 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Move Verific SVA importer to extra C++ source file | Clifford Wolf | 2018-02-18 | 1 | -0/+79 |
| Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
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