| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs | Clifford Wolf | 2019-08-06 | 1 | -0/+2 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | In RTLIL::Module::check(), check process invariants. | whitequark | 2019-06-19 | 1 | -1/+28 | |
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| * | Add rewrite_sigspecs2, Improve remove() wires | Clifford Wolf | 2019-05-15 | 1 | -7/+22 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Minor optimization to get_attribute_bool | Matthew Daiter | 2019-05-07 | 1 | -4/+8 | |
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| * | Merge remote-tracking branch 'origin/master' into clifford/specify | Eddie Hung | 2019-05-03 | 1 | -1/+1 | |
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| | * | Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970 | Clifford Wolf | 2019-04-30 | 1 | -1/+1 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 1 | -2/+2 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 1 | -1/+2 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add $specrule cells for $setup/$hold/$skew specify rules | Clifford Wolf | 2019-04-23 | 1 | -0/+15 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std ↵ | Clifford Wolf | 2019-04-23 | 1 | -2/+2 | |
| | | | | | | | | | | | | | nomenclature Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add InternalCellChecker support for $specify2 and $specify3 | Clifford Wolf | 2019-04-23 | 1 | -7/+21 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add specify parser | Clifford Wolf | 2019-04-23 | 1 | -0/+10 | |
| |/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Merge pull request #905 from christian-krieg/feature/python_bindings | Clifford Wolf | 2019-04-22 | 1 | -1/+97 | |
| |\ | | | | | Feature/python bindings | |||||
| | * | Global lists in rtlil.cc are now static objects | Benedikt Tutzer | 2019-04-03 | 1 | -10/+10 | |
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| | * | Merge remote-tracking branch 'origin/master' into feature/python_bindings | Benedikt Tutzer | 2019-03-28 | 1 | -3/+31 | |
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| | * | | added some checks if python is enabled to make sure everything compiles if ↵ | Benedikt Tutzer | 2018-08-20 | 1 | -4/+2 | |
| | | | | | | | | | | | | | python is disabled in the makefile | |||||
| | * | | Added Wrappers for: | Benedikt Tutzer | 2018-08-13 | 1 | -1/+31 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -IdString -Const -CaseRule -SwitchRule -SyncRule -Process -SigChunk -SigBit -SigSpec With all their member functions as well as the remaining member functions for Cell, Wire, Module and Design and static functions of rtlil.h | |||||
| | * | | added destructors for wires and cells | Benedikt Tutzer | 2018-07-10 | 1 | -0/+14 | |
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| | * | | removed debug output | Benedikt Tutzer | 2018-07-09 | 1 | -1/+0 | |
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| | * | | multiple designs can now exist independent from each other. ↵ | Benedikt Tutzer | 2018-07-09 | 1 | -0/+55 | |
| | | | | | | | | | | | | | Cells/Wires/Modules can now move to a different parent without referencing issues | |||||
| * | | | Add "wbflip" command | Clifford Wolf | 2019-04-20 | 1 | -2/+5 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Add "whitebox" attribute, add "read_verilog -wb" | Clifford Wolf | 2019-04-18 | 1 | -3/+3 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Add "read_ilang -lib" | Clifford Wolf | 2019-04-05 | 1 | -0/+24 | |
| | |/ |/| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signals | Clifford Wolf | 2019-03-23 | 1 | -1/+1 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add fmcombine pass | Clifford Wolf | 2019-03-15 | 1 | -2/+2 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Improve determinism of IdString DB for similar scripts | Clifford Wolf | 2019-03-11 | 1 | -0/+2 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Add FF support to wreduce | Clifford Wolf | 2019-02-20 | 1 | -0/+3 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | proc_clean: remove any empty cases if all cases use all-def compare. | whitequark | 2018-12-23 | 1 | -0/+10 | |
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| * | | Documentation improvements etc. | Ruben Undheim | 2018-10-13 | 1 | -3/+1 | |
| | | | | | | | | | | | | | | | | | | | - Mention new feature in the SystemVerilog section in the README file - Commented changes much better - Rename a few signals to make it clearer - Prevent warning for unused signals in an easier way - Add myself as copyright holder to 2 files - Fix one potential memory leak (delete 'wire' if not in modport) | |||||
| * | | Support for 'modports' for System Verilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -1/+1 | |
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| * | | Synthesis support for SystemVerilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -0/+15 | |
| |/ | | | | This time doing the changes mostly in AST before RTLIL generation | |||||
| * | Add $allconst and $allseq cell types | Clifford Wolf | 2018-02-23 | 1 | -1/+21 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Bugfix in hierarchy handling of blackbox module ports | Clifford Wolf | 2018-01-05 | 1 | -1/+3 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add RTLIL::Const::is_fully_ones() | Clifford Wolf | 2017-12-14 | 1 | -0/+11 | |
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| * | Add SigSpec::is_fully_ones() | Clifford Wolf | 2017-12-14 | 1 | -0/+15 | |
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| * | Add src arguments to all cell creator helper functions | Clifford Wolf | 2017-09-09 | 1 | -56/+91 | |
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| * | Update more stuff to use get_src_attribute() and set_src_attribute() | Clifford Wolf | 2017-09-01 | 1 | -1/+1 | |
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| * | Merge remote-tracking branch 'upstream/master' | Jason Lowdermilk | 2017-08-30 | 1 | -0/+16 | |
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| | * | Add {get,set}_src_attribute() methods on RTLIL::AttrObject | Clifford Wolf | 2017-08-30 | 1 | -0/+16 | |
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| * | | fix indent level | Jason Lowdermilk | 2017-08-30 | 1 | -2/+2 | |
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| * | | Add support for source line tracking through synthesis phase | Jason Lowdermilk | 2017-08-29 | 1 | -3/+4 | |
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| * | Add Const methods is_fully_zero(), is_fully_def(), and is_fully_undef() | Clifford Wolf | 2017-08-18 | 1 | -0/+33 | |
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| * | Add $_ANDNOT_ and $_ORNOT_ gates | Clifford Wolf | 2017-05-17 | 1 | -26/+30 | |
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| * | Add $live and $fair cell types, add support for s_eventually keyword | Clifford Wolf | 2017-02-25 | 1 | -1/+17 | |
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| * | Add $cover cell type and SVA cover() support | Clifford Wolf | 2017-02-04 | 1 | -1/+9 | |
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| * | Fix RTLIL::Memory::start_offset initialization | Clifford Wolf | 2017-01-25 | 1 | -0/+1 | |
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| * | Bugfix in RTLIL::SigSpec::remove2() | Clifford Wolf | 2016-12-31 | 1 | -3/+4 | |
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| * | Remember global declarations and defines accross read_verilog calls | Clifford Wolf | 2016-11-15 | 1 | -0/+2 | |
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| * | Added $anyseq cell type | Clifford Wolf | 2016-10-14 | 1 | -1/+10 | |
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| * | Added $ff and $_FF_ cell types | Clifford Wolf | 2016-10-12 | 1 | -0/+25 | |
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index : iCE40/yosys | |
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