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* | | Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-181-3/+3
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Add "read_ilang -lib"Clifford Wolf2019-04-051-0/+24
| |/ |/| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signalsClifford Wolf2019-03-231-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add fmcombine passClifford Wolf2019-03-151-2/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Improve determinism of IdString DB for similar scriptsClifford Wolf2019-03-111-0/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add FF support to wreduceClifford Wolf2019-02-201-0/+3
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | proc_clean: remove any empty cases if all cases use all-def compare.whitequark2018-12-231-0/+10
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* | Documentation improvements etc.Ruben Undheim2018-10-131-3/+1
| | | | | | | | | | | | | | | | | | - Mention new feature in the SystemVerilog section in the README file - Commented changes much better - Rename a few signals to make it clearer - Prevent warning for unused signals in an easier way - Add myself as copyright holder to 2 files - Fix one potential memory leak (delete 'wire' if not in modport)
* | Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-1/+1
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* | Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-0/+15
|/ | | | This time doing the changes mostly in AST before RTLIL generation
* Add $allconst and $allseq cell typesClifford Wolf2018-02-231-1/+21
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Bugfix in hierarchy handling of blackbox module portsClifford Wolf2018-01-051-1/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add RTLIL::Const::is_fully_ones()Clifford Wolf2017-12-141-0/+11
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* Add SigSpec::is_fully_ones()Clifford Wolf2017-12-141-0/+15
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* Add src arguments to all cell creator helper functionsClifford Wolf2017-09-091-56/+91
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* Update more stuff to use get_src_attribute() and set_src_attribute()Clifford Wolf2017-09-011-1/+1
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* Merge remote-tracking branch 'upstream/master'Jason Lowdermilk2017-08-301-0/+16
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| * Add {get,set}_src_attribute() methods on RTLIL::AttrObjectClifford Wolf2017-08-301-0/+16
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* | fix indent levelJason Lowdermilk2017-08-301-2/+2
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* | Add support for source line tracking through synthesis phaseJason Lowdermilk2017-08-291-3/+4
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* Add Const methods is_fully_zero(), is_fully_def(), and is_fully_undef()Clifford Wolf2017-08-181-0/+33
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* Add $_ANDNOT_ and $_ORNOT_ gatesClifford Wolf2017-05-171-26/+30
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* Add $live and $fair cell types, add support for s_eventually keywordClifford Wolf2017-02-251-1/+17
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* Add $cover cell type and SVA cover() supportClifford Wolf2017-02-041-1/+9
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* Fix RTLIL::Memory::start_offset initializationClifford Wolf2017-01-251-0/+1
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* Bugfix in RTLIL::SigSpec::remove2()Clifford Wolf2016-12-311-3/+4
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* Remember global declarations and defines accross read_verilog callsClifford Wolf2016-11-151-0/+2
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* Added $anyseq cell typeClifford Wolf2016-10-141-1/+10
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* Added $ff and $_FF_ cell typesClifford Wolf2016-10-121-0/+25
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* Improvements in assertpmuxClifford Wolf2016-09-071-0/+16
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* Removed $aconst cell typeClifford Wolf2016-08-301-1/+1
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* Removed $predict againClifford Wolf2016-08-281-9/+1
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* Fixed handling of transparent bram rd ports on ROMsClifford Wolf2016-08-271-0/+1
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* Added $anyconst and $aconstClifford Wolf2016-07-271-0/+6
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* Added $initstate cell type and vlog functionClifford Wolf2016-07-211-0/+6
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* After reading the SV spec, using non-standard predict() instead of expect()Clifford Wolf2016-07-211-2/+2
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* Added basic support for $expect cellsClifford Wolf2016-07-131-8/+17
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* A few modifications after pull request commentsRuben Undheim2016-06-181-1/+1
| | | | | - Renamed Design::packages to Design::verilog_packages - No need to include ast.h in rtlil.h
* Added support for SystemVerilog packages with localparam definitionsRuben Undheim2016-06-181-0/+2
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* Improved support for $sop cellsClifford Wolf2016-06-171-1/+1
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* Added $sop cell type and "abc -sop"Clifford Wolf2016-06-171-0/+9
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* Added addBufGate module methodClifford Wolf2016-02-021-0/+1
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* rtlil: Improve performance of SigSpec::extract(SigSpec, SigSpec*)Rick Altherr2016-01-311-2/+31
| | | | | | | | Converting to a pool<SigBit> is fairly expensive due to inserts somewhat frequently causing rehashing. Instead, walk through the pattern SigSpec directly on a chunk-by-chunk basis and apply it to this SigSpec's individual bits. Using chunks for the pattern minimizes the number of iterations in the outer loop.
* rtlil: speed up SigSpec::sort_and_unify()Rick Altherr2016-01-311-1/+11
| | | | | | | | | | std::set<> internally is often a red-black tree which is fairly expensive to create but fast to lookup. In the case of sort_and_unify(), a set<> is constructed as a temporary object to attempt to speed up lookups. Being a temporarily, however, the cost of creation far outweights the lookup improvement and is a net performance loss. Instead, sort the vector<> that already exists and then apply std::unique().
* rtlil: improve performance of SigSpec::replace(SigSpec, SigSpec, SigSpec*)Rick Altherr2016-01-311-6/+14
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* rtlil: improve performance of SigSpec::remove2(SigSpec, SigSpec*)Rick Altherr2016-01-311-2/+29
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* rtlil: rewrite remove2() to avoid copyingRick Altherr2016-01-301-45/+18
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* rtlil: duplicate remove2() for std::set<>Rick Altherr2016-01-291-0/+39
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* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-251-14/+14
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* renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()Clifford Wolf2015-10-241-12/+11
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