aboutsummaryrefslogtreecommitdiffstats
path: root/kernel/rtlil.h
Commit message (Collapse)AuthorAgeFilesLines
...
* | Merge pull request #2086 from rswarbrick/sigbitwhitequark2020-05-281-2/+1
|\ \ | | | | | | Use default copy constructor for RTLIL::SigBit
| * | Use default copy constructor for RTLIL::SigBitRupert Swarbrick2020-05-261-2/+1
| |/ | | | | | | | | | | | | | | | | | | | | There was a handwritten copy constructor, which I'm not sure was actually legal C++ (it unconditionally read from the 'data' member of a union, which wouldn't have been written if wire was true). It was also a bit less efficient than the constructor you get from the compiler by default (which is allowed to just copy the memory). This gives a marginal (~0.25%) decrease in code size when compiled with GCC 9.3.
* / Use c_str(), not str() for IdString/std::string == and != operatorsRupert Swarbrick2020-05-261-2/+2
|/ | | | | | | | | | | | | | | These operators work by fetching the string from the global string table and then comparing with the std::string that was passed in as rhs. Using str() means that we create a std::string (strlen; malloc; memcpy), compare for equality (another memcmp if they have the same length) and then finally free the string. Using c_str() means that we pass the const char* straight to std::string's equality operator. This ends up as a call to std::string::compare (the const char* flavour), which is essentially strcmp.
* ilang, ast: Store parameter order and default value information.Marcelina Kościelnicka2020-04-211-1/+2
| | | | Fixes #1819, #1820.
* rtlil: add AttrObject::has_attribute.whitequark2020-04-161-0/+2
|
* rtlil: add AttrObject::{get,set}_string_attribute.whitequark2020-04-161-2/+9
| | | | And make {get,set}_src_attribute use those functions.
* Merge pull request #1858 from YosysHQ/eddie/fix1856Eddie Hung2020-04-091-1/+1
|\ | | | | kernel: include "kernel/constids.inc"
| * kernel: include "kernel/constids.inc" instead of "constids.inc"Eddie Hung2020-04-091-1/+1
| |
* | [NFCI] Deduplicate builtin FF cell types listMarcelina Kościelnicka2020-04-091-0/+2
|/ | | | | | | | | A few passes included the same list of FF cell types. Make it a global const instead. The zinit pass also seems to include a list like that, but given that it seems to be completely broken at the time (see #1568 discussion), I'm going to pretend I didn't see that.
* kernel: IdString::in(const IdString &) as per @TjoppenEddie Hung2020-04-021-1/+1
|
* kernel: fix formatting (thanks @boqwxp)Eddie Hung2020-04-021-6/+4
|
* kernel: use C++11 fold hack to prevent recursionEddie Hung2020-04-021-3/+8
|
* Revert "kernel: IdString:in() to use perfect forwarding"Eddie Hung2020-04-021-2/+2
| | | | This reverts commit 7b2a85aedf24affc2e1202c78e70e6a317f5bf29.
* kernel: separate IdString::put_reference() out to help inliningEddie Hung2020-04-021-1/+4
|
* kernel: IdString:in() to use perfect forwardingEddie Hung2020-04-021-2/+2
|
* kernel: Use constids.inc for global/constant IdStringsEddie Hung2020-04-021-5/+3
|
* Merge pull request #1845 from YosysHQ/eddie/kernel_speedupEddie Hung2020-04-021-181/+191
|\ | | | | kernel: speedup by using more pass-by-const-ref
| * kernel: pass-by-value into Design::scratchpad_set_string() tooEddie Hung2020-03-271-1/+1
| |
| * kernel: Cell::set{Port,Param}() to pass by value, but use std::moveEddie Hung2020-03-261-2/+2
| | | | | | | | Otherwise cell->setPort(ID::A, cell->getPort(ID::B)) could be invalid
| * kernel: SigSpec copies to not trigger pack()Eddie Hung2020-03-181-1/+1
| |
| * kernel: more pass by const ref, more speedupsEddie Hung2020-03-181-180/+180
| |
| * kernel: SigSpec use more const& + overloads to prevent implicit SigSpecEddie Hung2020-03-131-7/+13
| |
| * kernel: optimise Module::remove(const pool<RTLIL::Wire*>()Eddie Hung2020-03-121-0/+4
| |
* | Add support for SystemVerilog-style `define to Verilog frontendRupert Swarbrick2020-03-271-1/+4
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | This patch should support things like `define foo(a, b = 3, c) a+b+c `foo(1, ,2) which will evaluate to 1+3+2. It also spots mistakes like `foo(1) (the 3rd argument doesn't have a default value, so a call site is required to set it). Most of the patch is a simple parser for the format in preproc.cc, but I've also taken the opportunity to wrap up the "name -> definition" map in a type, rather than use multiple std::map's. Since this type needs to be visible to code that touches defines, I've pulled it (and the frontend_verilog_preproc declaration) out into a new file at frontends/verilog/preproc.h and included that where necessary. Finally, the patch adds a few tests in tests/various to check that we are parsing everything correctly.
* Add and use SigSpec::reverse()Eddie Hung2020-01-281-0/+2
|
* Add RTLIL::constpad, init by yosys_setup(); use for abc9Eddie Hung2020-01-081-0/+2
|
* Add Const::{begin,end,empty}()Eddie Hung2019-10-041-0/+3
|
* Add YOSYS_NO_IDS_REFCNT configuration macroClifford Wolf2019-08-111-1/+22
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Use ID() in kernel/*, add simple ID:: hack (to be improved upon later)Clifford Wolf2019-08-111-3/+11
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* More improvements and cleanups in IdString subsystemClifford Wolf2019-08-111-36/+52
| | | | | | | | | - better use of "inline" keyword - deprecate "sticky" IDs feature - improve handling of empty ID - add move constructor Signed-off-by: Clifford Wolf <clifford@clifford.at>
* RTLIL::S{0,1} -> State::S{0,1} for headersEddie Hung2019-08-071-1/+1
|
* Merge remote-tracking branch 'origin/master' into eddie/cleanupEddie Hung2019-08-071-0/+2
|\
| * Add SigSpec::extract_end() convenience functionEddie Hung2019-08-061-0/+1
| |
| * Merge remote-tracking branch 'origin/master' into eddie/wreduce_addEddie Hung2019-08-061-3/+21
| |\
| * | Add an SigSpec::at(offset, defval) convenience methodEddie Hung2019-07-191-0/+1
| | |
* | | Fix typosEddie Hung2019-08-061-2/+2
| | |
* | | Use IdString::begins_with()Eddie Hung2019-08-061-3/+7
| |/ |/|
* | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-061-0/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | replaced std::iterator with using statementsJakob Wenzel2019-07-251-6/+6
| |
* | made ObjectIterator extend std::iteratorJakob Wenzel2019-07-241-2/+18
|/ | | | this makes it possible to use std algorithms on them
* Allow attributes on individual switch cases in RTLIL.whitequark2019-07-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The parser changes are slightly awkward. Consider the following IL: process $0 <point 1> switch \foo <point 2> case 1'1 assign \bar \baz <point 3> ... case end end Before this commit, attributes are valid in <point 1>, and <point 3> iff it is immediately followed by a `switch`. (They are essentially attached to the switch.) But, after this commit, and because switch cases do not have an ending delimiter, <point 3> becomes ambiguous: the attribute could attach to either the following `case`, or to the following `switch`. This isn't expressible in LALR(1) and results in a reduce/reduce conflict. To address this, attributes inside processes are now valid anywhere inside the process: in <point 1> and <point 3> a part of case body, and in <point 2> as a separate rule. As a consequence, attributes can now precede `assign`s, which is made illegal in the same way it is illegal to attach attributes to `connect`. Attributes are tracked separately from the parser state, so this does not affect collection of attributes at all, other than allowing them on `case`s. The grammar change serves purely to allow attributes in more syntactic places.
* Undo iterator based Module::remove() for cells, as containers will notEddie Hung2019-06-271-1/+0
| | | | invalidate
* Fix leak removing cells during ABC integration; also preserve attrEddie Hung2019-06-171-0/+1
|
* Further cleanup based on @daveshah1Eddie Hung2019-06-141-0/+6
|
* Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-121-1/+65
|\
| * Refactor hierarchy wand/wor handlingClifford Wolf2019-05-281-0/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Add rewrite_sigspecs2, Improve remove() wiresClifford Wolf2019-05-151-0/+60
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge pull request #991 from kristofferkoch/gcc9-warningsClifford Wolf2019-05-081-0/+3
| |\ | | | | | | Fix all warnings that occurred when compiling with gcc9
| | * Fix all warnings that occurred when compiling with gcc9Kristoffer Ellersgaard Koch2019-05-081-0/+3
| | |
| * | Improve write_verilog specify supportClifford Wolf2019-05-041-1/+1
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-09 09:47:26 +0000