iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Use feedback path for MACC	Eddie Hung	2019-09-03	1	-15/+21
*	autoremove ffM	Eddie Hung	2019-08-30	1	-0/+1
*	ffM before addAB	Eddie Hung	2019-08-30	1	-1/+1
*	Another oops	Eddie Hung	2019-08-30	1	-1/+1
*	Update commented out	Eddie Hung	2019-08-30	1	-1/+1
*	Add support for ffM	Eddie Hung	2019-08-30	1	-0/+12
*	Perform C -> PCIN optimisation after pattern matcher	Eddie Hung	2019-08-13	1	-10/+57
*	Rename to XilinxDspPass	Eddie Hung	2019-08-13	1	-3/+3
*	Pack partial-product adder DSP48E1 packing	Eddie Hung	2019-08-09	1	-5/+17
*	Remove muxY and ffY for now	Eddie Hung	2019-08-08	1	-5/+5
*	Disable $dffe	Eddie Hung	2019-08-08	1	-8/+8
*	Pack P register properly	Eddie Hung	2019-08-01	1	-2/+4
*	Fine tune ice40_dsp.pmg, add support for packing subsets of registers	Eddie Hung	2019-07-19	1	-1/+1
*	Do not autoremove ffP aor muxP	Eddie Hung	2019-07-18	1	-2/+0
*	Improve pattern matcher to match subsets of $dffe? cells	Eddie Hung	2019-07-18	1	-2/+8
*	Improve A/B reg packing	Eddie Hung	2019-07-18	1	-0/+3
*	Do not autoremove A/B registers since they might have other consumers	Eddie Hung	2019-07-18	1	-2/+0
*	Pattern matcher to check pool of bits, not exactly	Eddie Hung	2019-07-17	1	-3/+9
*	Signed extension	Eddie Hung	2019-07-16	1	-2/+2
*	Add support {A,B,P}REG packing	Eddie Hung	2019-07-16	1	-26/+42
*	Add xilinx_dsp for register packing	Eddie Hung	2019-07-15	1	-0/+120