iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Use feedback path for MACC	Eddie Hung	2019-09-03	1	-15/+21
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*	autoremove ffM	Eddie Hung	2019-08-30	1	-0/+1
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*	ffM before addAB	Eddie Hung	2019-08-30	1	-1/+1
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*	Another oops	Eddie Hung	2019-08-30	1	-1/+1
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*	Update commented out	Eddie Hung	2019-08-30	1	-1/+1
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*	Add support for ffM	Eddie Hung	2019-08-30	1	-0/+12
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*	Perform C -> PCIN optimisation after pattern matcher	Eddie Hung	2019-08-13	1	-10/+57
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*	Rename to XilinxDspPass	Eddie Hung	2019-08-13	1	-3/+3
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*	Pack partial-product adder DSP48E1 packing	Eddie Hung	2019-08-09	1	-5/+17
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*	Remove muxY and ffY for now	Eddie Hung	2019-08-08	1	-5/+5
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*	Disable $dffe	Eddie Hung	2019-08-08	1	-8/+8
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*	Pack P register properly	Eddie Hung	2019-08-01	1	-2/+4
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*	Fine tune ice40_dsp.pmg, add support for packing subsets of registers	Eddie Hung	2019-07-19	1	-1/+1
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*	Do not autoremove ffP aor muxP	Eddie Hung	2019-07-18	1	-2/+0
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*	Improve pattern matcher to match subsets of $dffe? cells	Eddie Hung	2019-07-18	1	-2/+8
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*	Improve A/B reg packing	Eddie Hung	2019-07-18	1	-0/+3
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*	Do not autoremove A/B registers since they might have other consumers	Eddie Hung	2019-07-18	1	-2/+0
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*	Pattern matcher to check pool of bits, not exactly	Eddie Hung	2019-07-17	1	-3/+9
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*	Signed extension	Eddie Hung	2019-07-16	1	-2/+2
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*	Add support {A,B,P}REG packing	Eddie Hung	2019-07-16	1	-26/+42
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*	Add xilinx_dsp for register packing	Eddie Hung	2019-07-15	1	-0/+120