| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | | * | | | | | | | | | | | | | | | | | Rename $currQ to $abc9_currQ | Eddie Hung | 2019-10-07 | 1 | -46/+46 | |
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| | | * | | | | | | | | | | | | | | | | | Update comments in abc9_map.v | Eddie Hung | 2019-10-07 | 1 | -131/+57 | |
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| | | * | | | | | | | | | | | | | | | | | Remove -D_ABC9 | Eddie Hung | 2019-10-07 | 1 | -2/+0 | |
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| | | * | | | | | | | | | | | | | | | | | Do not require changes to cells_sim.v; try and work out comb model | Eddie Hung | 2019-10-05 | 4 | -230/+200 | |
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| | | * | | | | | | | | | | | | | | | | | abc -> abc9 | Eddie Hung | 2019-10-04 | 1 | -3/+3 | |
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| | | * | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-10-04 | 4 | -181/+9 | |
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| | | * | | | | | | | | | | | | | | | | | | Use read_args for read_verilog | Eddie Hung | 2019-10-04 | 1 | -3/+6 | |
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| | | * | | | | | | | | | | | | | | | | | | Fix merge issues | Eddie Hung | 2019-10-04 | 2 | -9/+10 | |
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| | | * | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff | Eddie Hung | 2019-10-04 | 31 | -278/+294 | |
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| | | * \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-10-03 | 6 | -2/+184 | |
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| | | * | | | | | | | | | | | | | | | | | | | | English | Eddie Hung | 2019-10-03 | 1 | -3/+3 | |
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| | | * | | | | | | | | | | | | | | | | | | | | More fixes | Eddie Hung | 2019-10-01 | 1 | -16/+16 | |
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| | | * | | | | | | | | | | | | | | | | | | | | Escape Verilog identifiers for legality outside of Yosys | Eddie Hung | 2019-10-01 | 1 | -48/+48 | |
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| | | * | | | | | | | | | | | | | | | | | | | | Remove need for $currQ port connection | Eddie Hung | 2019-09-30 | 2 | -111/+118 | |
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| | | * | | | | | | | | | | | | | | | | | | | | Add explanation to abc_map.v | Eddie Hung | 2019-09-30 | 1 | -0/+16 | |
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| | | * | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-30 | 8 | -124/+122 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | Missing endmodule | Eddie Hung | 2019-09-29 | 1 | -0/+1 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-29 | 19 | -31/+3401 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | FDCE_1 does not have IS_CLR_INVERTED | Eddie Hung | 2019-09-29 | 1 | -1/+1 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-29 | 1 | -1/+1 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | | Big rework; flop info now mostly in cells_sim.v | Eddie Hung | 2019-09-28 | 6 | -295/+314 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-27 | 57 | -1594/+22196 | |
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| | | * | | | | | | | | | | | | | | | | | | | | | | | | Revert "Remove sequential extension" | Eddie Hung | 2019-08-20 | 6 | -17/+359 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 091bf4a18b2f4bf84fe62b61577c88d961468b3c. | |||||
| | * | | | | | | | | | | | | | | | | | | | | | | | | | Fix DSP48E1 sim | Eddie Hung | 2020-01-06 | 1 | -3/+3 | |
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| * / | | | | | | | | | | | | | | | | | | | | | | | | Re-enable &mfs for synth_{ecp5,xilinx} | Eddie Hung | 2020-01-06 | 2 | -3/+2 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1617 from YosysHQ/eddie/abc9_dsp_refactor | Eddie Hung | 2020-01-06 | 5 | -1653/+507 | |
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / / |/| | | | | | | | | | | | | | | | | | | | | | | | Refactor abc9's DSP48E1 handling | |||||
| | * | | | | | | | | | | | | | | | | | | | | | | | Wrap arrival functions inside `YOSYS too | Eddie Hung | 2020-01-06 | 1 | -0/+2 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | Fix return value of arrival time functions, fix word | Eddie Hung | 2020-01-06 | 1 | -18/+14 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | Drive $[ABCD] explicitly | Eddie Hung | 2020-01-02 | 1 | -15/+21 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/abc9_dsp_refactor | Eddie Hung | 2020-01-02 | 13 | -43/+43 | |
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / / | | |/| | | | | | | | | | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | | | | | | | | | | | | ifndef __ICARUS__ -> ifdef YOSYS | Eddie Hung | 2020-01-01 | 1 | -2/+2 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | Rework abc9's DSP48E1 model | Eddie Hung | 2020-01-01 | 5 | -1656/+506 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | | Valid to have attribute starting with SB_CARRY. | Miodrag Milanovic | 2020-01-04 | 1 | -0/+2 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1604 from whitequark/unify-ram-naming | whitequark | 2020-01-02 | 18 | -40/+67 | |
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | |_|/ / / / / / / / / / / / / / / / / / / / / / |/| | | | | | | | | | | | | | | | | | | | | | | | Harmonize BRAM/LUTRAM descriptions across all of Yosys | |||||
| | * | | | | | | | | | | | | | | | | | | | | | | | Harmonize BRAM/LUTRAM descriptions across all of Yosys. | whitequark | 2020-01-01 | 18 | -40/+67 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit: * renames all remaining instances of "DRAM" (which is ambiguous) to "LUTRAM" (which is not), finishing the work started in the commit 698ab9be; * renames memory rule files to brams.txt/lutrams.txt; * adds/renames script labels map_bram/map_lutram; * extracts where necessary script labels map_ffram and map_gates; * adds where necessary options -nobram/-nolutram. The end result is that BRAM/LUTRAM/FFRAM aspects of every target are now consistent with each other. Per architecture: * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add :map_lutram, :map_ffram, :map_gates * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram, :map_gates * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt, rename -nodram→-nolutram (-nodram still recognized), rename :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates | |||||
| * | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1601 from YosysHQ/eddie/synth_retime | Eddie Hung | 2020-01-02 | 12 | -37/+37 | |
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "abc -dff" to no longer retime by default | |||||
| | * | | | | | | | | | | | | | | | | | | | | | | | | Update doc that "-retime" calls abc with "-dff -D 1" | Eddie Hung | 2019-12-30 | 11 | -12/+12 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | Disable synth_gowin -abc9 as it offers no advantages yet | Eddie Hung | 2019-12-30 | 1 | -12/+12 | |
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| | * | | | | | | | | | | | | | | | | | | | | | | | | Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well"" | Eddie Hung | 2019-12-30 | 11 | -13/+13 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 6008bb7002f874e5c748eaa2050e7b6c17b32745. | |||||
| * | | | | | | | | | | | | | | | | | | | | | | | | | ifdef __ICARUS__ -> ifndef YOSYS | Eddie Hung | 2020-01-01 | 1 | -6/+6 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | | Fix anlogic async flop mapping | Eddie Hung | 2020-01-01 | 1 | -8/+8 | |
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| * | | | | | | | | | | | | | | | | | | | | | | | Update timings for Xilinx S7 cells | Eddie Hung | 2019-12-30 | 1 | -15/+35 | |
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| * | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1589 from YosysHQ/iopad_default | Miodrag Milanović | 2019-12-30 | 1 | -11/+6 | |
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | |/ / / / / / / / / / / / / / / / / / / / / |/| | | | | | | | | | | | | | | | | | | | | | Make iopad option default for all xilinx flows | |||||
| | * | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into iopad_default | Miodrag Milanovic | 2019-12-28 | 8 | -10/+368 | |
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / | | |/| | | | | | | | | | | | | | | | | | | | ||||||
| | * | | | | | | | | | | | | | | | | | | | | | Addressed review comments | Miodrag Milanovic | 2019-12-21 | 1 | -2/+3 | |
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| | * | | | | | | | | | | | | | | | | | | | | | iopad no op for compatibility with old scripts | Miodrag Milanovic | 2019-12-21 | 1 | -0/+3 | |
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| | * | | | | | | | | | | | | | | | | | | | | | Make iopad option default for all xilinx flows | Miodrag Milanovic | 2019-12-21 | 1 | -14/+5 | |
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| * | | | | | | | | | | | | | | | | | | | | | Nitpick cleanup for ecp5 | Eddie Hung | 2019-12-27 | 2 | -11/+3 | |
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| * | | | | | | | | | | | | | | | | | | | | Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen | Marcin Kościelnicki | 2019-12-25 | 3 | -3/+6 | |
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | xilinx_dsp: Initial DSP48A/DSP48A1 support. | |||||
| | * | | | | | | | | | | | | | | | | | | | | xilinx_dsp: Initial DSP48A/DSP48A1 support. | Marcin Kościelnicki | 2019-12-22 | 3 | -3/+6 | |
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index : iCE40/yosys | |
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