| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | | | | | | | | | | | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff | Eddie Hung | 2019-10-04 | 31 | -278/+294 | |
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| | * \ \ \ \ \ \ \ \ \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-10-03 | 6 | -2/+184 | |
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| | * | | | | | | | | | | | | | | | English | Eddie Hung | 2019-10-03 | 1 | -3/+3 | |
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| | * | | | | | | | | | | | | | | | More fixes | Eddie Hung | 2019-10-01 | 1 | -16/+16 | |
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| | * | | | | | | | | | | | | | | | Escape Verilog identifiers for legality outside of Yosys | Eddie Hung | 2019-10-01 | 1 | -48/+48 | |
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| | * | | | | | | | | | | | | | | | Remove need for $currQ port connection | Eddie Hung | 2019-09-30 | 2 | -111/+118 | |
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| | * | | | | | | | | | | | | | | | Add explanation to abc_map.v | Eddie Hung | 2019-09-30 | 1 | -0/+16 | |
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| | * | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-30 | 8 | -124/+122 | |
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| | * | | | | | | | | | | | | | | | | Missing endmodule | Eddie Hung | 2019-09-29 | 1 | -0/+1 | |
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| | * | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-29 | 19 | -31/+3401 | |
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| | * | | | | | | | | | | | | | | | | | FDCE_1 does not have IS_CLR_INVERTED | Eddie Hung | 2019-09-29 | 1 | -1/+1 | |
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| | * | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-29 | 1 | -1/+1 | |
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| | * | | | | | | | | | | | | | | | | | | Big rework; flop info now mostly in cells_sim.v | Eddie Hung | 2019-09-28 | 6 | -295/+314 | |
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| | * | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-27 | 57 | -1594/+22196 | |
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| | * | | | | | | | | | | | | | | | | | | | Revert "Remove sequential extension" | Eddie Hung | 2019-08-20 | 6 | -17/+359 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 091bf4a18b2f4bf84fe62b61577c88d961468b3c. | |||||
| * | | | | | | | | | | | | | | | | | | | | Update timings for Xilinx S7 cells | Eddie Hung | 2019-12-30 | 1 | -15/+35 | |
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| * | | | | | | | | | | | | | | | | | | | Merge pull request #1589 from YosysHQ/iopad_default | Miodrag Milanović | 2019-12-30 | 1 | -11/+6 | |
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make iopad option default for all xilinx flows | |||||
| | * \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into iopad_default | Miodrag Milanovic | 2019-12-28 | 8 | -10/+368 | |
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| | * | | | | | | | | | | | | | | | | | | | | Addressed review comments | Miodrag Milanovic | 2019-12-21 | 1 | -2/+3 | |
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| | * | | | | | | | | | | | | | | | | | | | | iopad no op for compatibility with old scripts | Miodrag Milanovic | 2019-12-21 | 1 | -0/+3 | |
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| | * | | | | | | | | | | | | | | | | | | | | Make iopad option default for all xilinx flows | Miodrag Milanovic | 2019-12-21 | 1 | -14/+5 | |
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| * | | | | | | | | | | | | | | | | | | | | Nitpick cleanup for ecp5 | Eddie Hung | 2019-12-27 | 2 | -11/+3 | |
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| * | | | | | | | | | | | | | | | | | | | Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen | Marcin Kościelnicki | 2019-12-25 | 3 | -3/+6 | |
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | xilinx_dsp: Initial DSP48A/DSP48A1 support. | |||||
| | * | | | | | | | | | | | | | | | | | | | xilinx_dsp: Initial DSP48A/DSP48A1 support. | Marcin Kościelnicki | 2019-12-22 | 3 | -3/+6 | |
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| * / / / / / / / / / / / / / / / / / / | xilinx: Test our DSP48A/DSP48A1 simulation models. | Marcin Kościelnicki | 2019-12-23 | 5 | -7/+362 | |
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| * | | | | | | | | | | | | | | | | / | Add abc9_arrival times for RAM{32,64}M | Eddie Hung | 2019-12-20 | 1 | -24/+10 | |
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| * | | | | | | | | | | | | | | | | | Add RAM{32,64}M to abc9_map.v | Eddie Hung | 2019-12-20 | 1 | -0/+78 | |
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| * | | | | | | | | | | | | | | | | | Revert "Optimise write_xaiger" | Eddie Hung | 2019-12-20 | 3 | -15/+0 | |
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| * | | | | | | | | | | | | | | | | | Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup | Eddie Hung | 2019-12-19 | 3 | -0/+15 | |
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Optimise write_xaiger | |||||
| | * | | | | | | | | | | | | | | | | | techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger | Eddie Hung | 2019-12-06 | 3 | -0/+15 | |
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| * | | | | | | | | | | | | | | | | | xilinx: Add simulation models for remaining CLB primitives. | Marcin Kościelnicki | 2019-12-19 | 3 | -156/+210 | |
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| * | | | | | | | | | | | | | | | | | xilinx_dffopt: Keep order of LUT inputs. | Marcin Kościelnicki | 2019-12-19 | 1 | -16/+30 | |
| | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | See rationale at https://github.com/YosysHQ/yosys/pull/1557#discussion_r359196549 | |||||
| * | | | | | | | | | | | | | | | | Merge pull request #1563 from YosysHQ/dave/async-prld | David Shah | 2019-12-18 | 2 | -4/+28 | |
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ecp5: Add support for mapping PRLD FFs | |||||
| | * | | | | | | | | | | | | | | | | ecp5: Add support for mapping PRLD FFs | David Shah | 2019-12-07 | 2 | -4/+28 | |
| | |/ / / / / / / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | | | | | | | | | | | | | | xilinx: Add xilinx_dffopt pass (#1557) | Marcin Kościelnicki | 2019-12-18 | 6 | -22/+389 | |
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| * | | | | | | | | | | | | | | | | xilinx: Improve flip-flop handling. | Marcin Kościelnicki | 2019-12-18 | 4 | -38/+228 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data. | |||||
| * | | | | | | | | | | | | | | | | Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram | Eddie Hung | 2019-12-16 | 3 | -12/+301 | |
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | xilinx: add LUTRAM rules for RAM32M, RAM64M | |||||
| | * \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into ↵ | Eddie Hung | 2019-12-16 | 1 | -2/+8 | |
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | eddie/xilinx_lutram | |||||
| | | * | | | | | | | | | | | | | | | | Populate DID/DOD even if unused | Eddie Hung | 2019-12-16 | 1 | -2/+8 | |
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| | * | | | | | | | | | | | | | | | | | Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q | Eddie Hung | 2019-12-16 | 2 | -6/+6 | |
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| | * | | | | | | | | | | | | | | | | Disable RAM16X1D match rule; carry-over from LUT4 arches | Eddie Hung | 2019-12-13 | 1 | -6/+9 | |
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| | * | | | | | | | | | | | | | | | | RAM64M8 to also have [5:0] for address | Eddie Hung | 2019-12-13 | 1 | -8/+8 | |
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| | * | | | | | | | | | | | | | | | | Add RAM32X6SDP and RAM64X3SDP modes | Eddie Hung | 2019-12-12 | 2 | -8/+120 | |
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| | * | | | | | | | | | | | | | | | | Fix RAM64M model to have 6 bit address bus | Eddie Hung | 2019-12-12 | 1 | -4/+4 | |
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| | * | | | | | | | | | | | | | | | | Add memory rules for RAM16X1D, RAM32M, RAM64M | Eddie Hung | 2019-12-12 | 2 | -0/+168 | |
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| * | | | | | | | | | | | | | | | | Add unconditional match blocks for force RAM | Eddie Hung | 2019-12-16 | 1 | -4/+36 | |
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| * | | | | | | | | | | | | | | | | Update xc7/xcu bram rules | Eddie Hung | 2019-12-16 | 1 | -8/+4 | |
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| * | | | | | | | | | | | | | | | | Removing fixed attribute value to !ramstyle rules | Diego H | 2019-12-15 | 1 | -4/+4 | |
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| * | | | | | | | | | | | | | | | | Merging attribute rules into a single match block; Adding tests | Diego H | 2019-12-15 | 1 | -18/+12 | |
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| * | | | | | | | | | | | | | | | | Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific | Diego H | 2019-12-13 | 1 | -0/+19 | |
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index : iCE40/yosys | |
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