aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs
Commit message (Collapse)AuthorAgeFilesLines
...
| | * | | | | | | | | | | | | | | | | | | | | | Escape Verilog identifiers for legality outside of YosysEddie Hung2019-10-011-48/+48
| | | | | | | | | | | | | | | | | | | | | | | |
| | * | | | | | | | | | | | | | | | | | | | | | Remove need for $currQ port connectionEddie Hung2019-09-302-111/+118
| | | | | | | | | | | | | | | | | | | | | | | |
| | * | | | | | | | | | | | | | | | | | | | | | Add explanation to abc_map.vEddie Hung2019-09-301-0/+16
| | | | | | | | | | | | | | | | | | | | | | | |
| | * | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-308-124/+122
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \
| | * | | | | | | | | | | | | | | | | | | | | | | Missing endmoduleEddie Hung2019-09-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | |
| | * | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-2919-31/+3401
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \
| | * | | | | | | | | | | | | | | | | | | | | | | | FDCE_1 does not have IS_CLR_INVERTEDEddie Hung2019-09-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | |
| | * | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-291-1/+1
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \
| | * | | | | | | | | | | | | | | | | | | | | | | | | Big rework; flop info now mostly in cells_sim.vEddie Hung2019-09-286-295/+314
| | | | | | | | | | | | | | | | | | | | | | | | | | |
| | * | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-2757-1594/+22196
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \
| | * | | | | | | | | | | | | | | | | | | | | | | | | | Revert "Remove sequential extension"Eddie Hung2019-08-206-17/+359
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 091bf4a18b2f4bf84fe62b61577c88d961468b3c.
| * | | | | | | | | | | | | | | | | | | | | | | | | | | Fix DSP48E1 simEddie Hung2020-01-061-3/+3
| | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | |
* / | | | | | | | | | | | | | | | | | | | | | | | | | Re-enable &mfs for synth_{ecp5,xilinx}Eddie Hung2020-01-062-3/+2
|/ / / / / / / / / / / / / / / / / / / / / / / / / /
* | | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1617 from YosysHQ/eddie/abc9_dsp_refactorEddie Hung2020-01-065-1653/+507
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / / / / |/| | | | | | | | | | | | | | | | | | | | | | | | | Refactor abc9's DSP48E1 handling
| * | | | | | | | | | | | | | | | | | | | | | | | | Wrap arrival functions inside `YOSYS tooEddie Hung2020-01-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | | | | | | | | | | Fix return value of arrival time functions, fix wordEddie Hung2020-01-061-18/+14
| | | | | | | | | | | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | | | | | | | | | | Drive $[ABCD] explicitlyEddie Hung2020-01-021-15/+21
| | | | | | | | | | | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/abc9_dsp_refactorEddie Hung2020-01-0213-43/+43
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / / / / | | |/| | | | | | | | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | | | | | | | | | | ifndef __ICARUS__ -> ifdef YOSYSEddie Hung2020-01-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | | | | | | | | | | Rework abc9's DSP48E1 modelEddie Hung2020-01-015-1656/+506
| | | | | | | | | | | | | | | | | | | | | | | | | |
* | | | | | | | | | | | | | | | | | | | | | | | | | Valid to have attribute starting with SB_CARRY.Miodrag Milanovic2020-01-041-0/+2
| |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | |
* | | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1604 from whitequark/unify-ram-namingwhitequark2020-01-0218-40/+67
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | |_|/ / / / / / / / / / / / / / / / / / / / / / / |/| | | | | | | | | | | | | | | | | | | | | | | | Harmonize BRAM/LUTRAM descriptions across all of Yosys
| * | | | | | | | | | | | | | | | | | | | | | | | Harmonize BRAM/LUTRAM descriptions across all of Yosys.whitequark2020-01-0118-40/+67
| | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit: * renames all remaining instances of "DRAM" (which is ambiguous) to "LUTRAM" (which is not), finishing the work started in the commit 698ab9be; * renames memory rule files to brams.txt/lutrams.txt; * adds/renames script labels map_bram/map_lutram; * extracts where necessary script labels map_ffram and map_gates; * adds where necessary options -nobram/-nolutram. The end result is that BRAM/LUTRAM/FFRAM aspects of every target are now consistent with each other. Per architecture: * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add :map_lutram, :map_ffram, :map_gates * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram, :map_gates * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt, rename -nodram→-nolutram (-nodram still recognized), rename :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
* | | | | | | | | | | | | | | | | | | | | | | | Merge pull request #1601 from YosysHQ/eddie/synth_retimeEddie Hung2020-01-0212-37/+37
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "abc -dff" to no longer retime by default
| * | | | | | | | | | | | | | | | | | | | | | | | Update doc that "-retime" calls abc with "-dff -D 1"Eddie Hung2019-12-3011-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | | | | | | | | | Disable synth_gowin -abc9 as it offers no advantages yetEddie Hung2019-12-301-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | | | | | | | | | Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""Eddie Hung2019-12-3011-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 6008bb7002f874e5c748eaa2050e7b6c17b32745.
* | | | | | | | | | | | | | | | | | | | | | | | | ifdef __ICARUS__ -> ifndef YOSYSEddie Hung2020-01-011-6/+6
| |_|/ / / / / / / / / / / / / / / / / / / / / / |/| | | | | | | | | | | | | | | | | | | | | | |
* | | | | | | | | | | | | | | | | | | | | | | | Fix anlogic async flop mappingEddie Hung2020-01-011-8/+8
| |/ / / / / / / / / / / / / / / / / / / / / / |/| | | | | | | | | | | | | | | | | | | | | |
* | | | | | | | | | | | | | | | | | | | | | | Update timings for Xilinx S7 cellsEddie Hung2019-12-301-15/+35
| |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / / |/| | | | | | | | | | | | | | | | | | | | |
* | | | | | | | | | | | | | | | | | | | | | Merge pull request #1589 from YosysHQ/iopad_defaultMiodrag Milanović2019-12-301-11/+6
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | |/ / / / / / / / / / / / / / / / / / / / / |/| | | | | | | | | | | | | | | | | | | | | Make iopad option default for all xilinx flows
| * | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into iopad_defaultMiodrag Milanovic2019-12-288-10/+368
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / | | |/| | | | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | | | | | | Addressed review commentsMiodrag Milanovic2019-12-211-2/+3
| | | | | | | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | | | | | | iopad no op for compatibility with old scriptsMiodrag Milanovic2019-12-211-0/+3
| | | | | | | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | | | | | | Make iopad option default for all xilinx flowsMiodrag Milanovic2019-12-211-14/+5
| | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / | |/| | | | | | | | | | | | | | | | | | |
* | | | | | | | | | | | | | | | | | | | | Nitpick cleanup for ecp5Eddie Hung2019-12-272-11/+3
| |/ / / / / / / / / / / / / / / / / / / |/| | | | | | | | | | | | | | | | | | |
* | | | | | | | | | | | | | | | | | | | Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgenMarcin Kościelnicki2019-12-253-3/+6
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | xilinx_dsp: Initial DSP48A/DSP48A1 support.
| * | | | | | | | | | | | | | | | | | | | xilinx_dsp: Initial DSP48A/DSP48A1 support.Marcin Kościelnicki2019-12-223-3/+6
| |/ / / / / / / / / / / / / / / / / / /
* / / / / / / / / / / / / / / / / / / / xilinx: Test our DSP48A/DSP48A1 simulation models.Marcin Kościelnicki2019-12-235-7/+362
|/ / / / / / / / / / / / / / / / / / /
* | | | | | | | | | | | | | | | | / / Add abc9_arrival times for RAM{32,64}MEddie Hung2019-12-201-24/+10
| |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / |/| | | | | | | | | | | | | | | | |
* | | | | | | | | | | | | | | | | | Add RAM{32,64}M to abc9_map.vEddie Hung2019-12-201-0/+78
| | | | | | | | | | | | | | | | | |
* | | | | | | | | | | | | | | | | | Revert "Optimise write_xaiger"Eddie Hung2019-12-203-15/+0
| | | | | | | | | | | | | | | | | |
* | | | | | | | | | | | | | | | | | Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanupEddie Hung2019-12-193-0/+15
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Optimise write_xaiger
| * | | | | | | | | | | | | | | | | | techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaigerEddie Hung2019-12-063-0/+15
| | |_|_|_|_|_|_|_|_|_|_|_|_|/ / / / | |/| | | | | | | | | | | | | | | |
* | | | | | | | | | | | | | | | | | xilinx: Add simulation models for remaining CLB primitives.Marcin Kościelnicki2019-12-193-156/+210
| | | | | | | | | | | | | | | | | |
* | | | | | | | | | | | | | | | | | xilinx_dffopt: Keep order of LUT inputs.Marcin Kościelnicki2019-12-191-16/+30
| |_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | See rationale at https://github.com/YosysHQ/yosys/pull/1557#discussion_r359196549
* | | | | | | | | | | | | | | | | Merge pull request #1563 from YosysHQ/dave/async-prldDavid Shah2019-12-182-4/+28
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ecp5: Add support for mapping PRLD FFs
| * | | | | | | | | | | | | | | | | ecp5: Add support for mapping PRLD FFsDavid Shah2019-12-072-4/+28
| |/ / / / / / / / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | | | | | | | | | | xilinx: Add xilinx_dffopt pass (#1557)Marcin Kościelnicki2019-12-186-22/+389
| | | | | | | | | | | | | | | | |
* | | | | | | | | | | | | | | | | xilinx: Improve flip-flop handling.Marcin Kościelnicki2019-12-184-38/+228
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data.
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-06 13:46:12 +0000