| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | Try to convert extended name to a name | Tristan Gingold | 2020-11-18 | 1 | -1/+31 | |
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| * | ci: disable trigger | eine | 2020-11-12 | 1 | -9/+12 | |
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| * | ci: add command-line arguments | Rodrigo Alejandro Melo | 2020-10-03 | 2 | -1/+33 | |
| | | | | | - add *.edif and *.ilang files to .gitignore | |||||
| * | '%' is not supported by Xilinx ISE edif2ngc. Fix #134 | eine | 2020-10-02 | 1 | -1/+2 | |
| | | | | | Authored-By: Tristan Gingold <tgingold@free.fr> | |||||
| * | testsuite/issues: renames pr61 to issue61 | Tristan Gingold | 2020-09-27 | 2 | -0/+0 | |
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| * | testsuite/issues: adjust pr61 | Tristan Gingold | 2020-09-27 | 1 | -1/+2 | |
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| * | testsuite: add a test for ghdl/ghdl#1421 | Tristan Gingold | 2020-09-27 | 3 | -0/+133 | |
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| * | readme: update shields/badges | eine | 2020-08-31 | 1 | -2/+2 | |
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| * | ci: fix synth_formal.dockerfile URL | eine | 2020-07-24 | 1 | -1/+1 | |
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| * | ci: dispatch after push to 'master' only | eine | 2020-06-05 | 1 | -0/+1 | |
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| * | ci: trigger repository_dispatch in ghdl/docker | eine | 2020-06-05 | 1 | -0/+7 | |
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| * | Add formal tests for mod/rem | Xiretza | 2020-05-30 | 3 | -1/+113 | |
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| * | Fix signed modulo behaviour | Xiretza | 2020-05-30 | 1 | -4/+5 | |
| | | | | | | | | | | Yosys' $mod cell is the modulo of truncating division, known as "rem" in VHDL. The new $modfloor cell is the modulo of flooring division, known as "mod" in VHDL. "mod" now synthesizes correctly for negative numbers. | |||||
| * | Fix testsuite failing on second run | Xiretza | 2020-05-30 | 1 | -1/+1 | |
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| * | Add reduce_xor support to the Yosys plugin | rlee287 | 2020-05-28 | 1 | -0/+4 | |
| | | | | | This is a followup for ghdl/ghdl issue 1342 | |||||
| * | Re-add instructions to make a static build. | Tristan Gingold | 2020-05-23 | 2 | -0/+45 | |
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| * | Add a test for ghdl/ghdl#1318 | Tristan Gingold | 2020-05-23 | 2 | -0/+51 | |
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| * | Adjust a test. | Tristan Gingold | 2020-05-23 | 1 | -1/+1 | |
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| * | ghdl.cc: import attributes on memory. For ghdl/ghdl#1318 | Tristan Gingold | 2020-05-23 | 1 | -1/+19 | |
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| * | README.md: remove static build instructions. | Tristan Gingold | 2020-05-22 | 2 | -64/+0 | |
| | | | | | Was not working anymore. | |||||
| * | Add a test for ghdl/ghdl#1314 | Tristan Gingold | 2020-05-16 | 2 | -0/+184 | |
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| * | Add a test for inout port with default value. | Tristan Gingold | 2020-05-16 | 2 | -0/+23 | |
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| * | ghdl.cc: handle Id_Iinout | Tristan Gingold | 2020-05-16 | 1 | -0/+2 | |
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| * | Add another test from ghdl/ghdl#1309 | Tristan Gingold | 2020-05-14 | 3 | -0/+116 | |
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| * | Add test from ghdl/ghdl#1309 | Tristan Gingold | 2020-05-14 | 6 | -0/+749 | |
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| * | testsuite: add test from ghdl/ghdl#1307 | Tristan Gingold | 2020-05-14 | 6 | -0/+432 | |
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| * | Add formal test for pmux gate | Xiretza | 2020-05-14 | 3 | -1/+59 | |
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| * | Fix ordering of $pmux ports | Xiretza | 2020-05-14 | 1 | -2/+2 | |
| | | | | | | | | | For Id_Pmux, IN(2+n) corresponds to s(n). For $pmux, B[n*WIDTH-1:(n-1)*WIDTH] corresponds to S[n]. Therefore, the inputs need to be appended in ascending order, such that IN(2) is assigned to B[WIDTH-1:0], IN(3) to B[2*WIDTH-1:WIDTH], etc. | |||||
| * | ghdl.cc: implement id_pmux | Tristan Gingold | 2020-05-09 | 1 | -12/+22 | |
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| * | Add test for ghdl#1238 | Tristan Gingold | 2020-04-23 | 2 | -0/+30 | |
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| * | handle Id_Tri and Id_Resolver | Tristan Gingold | 2020-04-23 | 1 | -0/+9 | |
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| * | ghdl.cc: adjust for recent yosys. Fix #107 | Tristan Gingold | 2020-04-23 | 1 | -1/+1 | |
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| * | readme: fix docker usage | eine | 2020-04-19 | 1 | -2/+4 | |
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| * | Improve examples for Lattice iCEstick | Aimylios | 2020-04-19 | 16 | -5/+45 | |
| | | | | | | | | - move "leds" examples to subdirectory - add Makefile - add *.json files to .gitignore - adjust README.md and fix some typos | |||||
| * | Add tests/examples for dff (both pos and neg edge). | Tristan Gingold | 2020-04-15 | 5 | -0/+116 | |
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| * | ghdl.cc: adjust for edge handle (ghdl#1227) | Tristan Gingold | 2020-04-15 | 1 | -16/+53 | |
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| * | update README | umarcor | 2020-04-10 | 1 | -32/+26 | |
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| * | ghdl.cc: avoid duplicate blackboxes. | Tristan Gingold | 2020-04-09 | 1 | -1/+4 | |
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| * | Add a test for asynchronous reset dff. | Tristan Gingold | 2020-04-07 | 3 | -0/+43 | |
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| * | Adjust test with incorrect value. | Tristan Gingold | 2020-04-07 | 2 | -2/+2 | |
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| * | Add support for non-constant asynchronous reset dff. | Tristan Gingold | 2020-04-07 | 1 | -5/+29 | |
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| * | Add a test for #102 | Tristan Gingold | 2020-04-07 | 2 | -0/+34 | |
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| * | Add support for smod. Fix #102 | Tristan Gingold | 2020-04-07 | 1 | -0/+2 | |
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| * | Adjust ecp5_versa tests. Wrappers for verilog modules are not needed anymore. | Tristan Gingold | 2020-03-31 | 5 | -78/+73 | |
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| * | Handle Id_User_Parameters: add parameters to gates. | Tristan Gingold | 2020-03-31 | 1 | -21/+60 | |
| | | | | | This allows easy interfacing with verilog modules. | |||||
| * | Add regression test for versa_ecp5 | Tristan Gingold | 2020-03-31 | 1 | -0/+25 | |
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| * | Add a test for #96 | Tristan Gingold | 2020-03-29 | 2 | -0/+33 | |
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| * | Add support for inout gate. Fix #96 | Tristan Gingold | 2020-03-29 | 1 | -3/+39 | |
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| * | Fixed URL of the ghdl/synth Docker image | Rodrigo Alejandro Melo | 2020-03-27 | 1 | -1/+3 | |
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| * | Add min/max gates | Xiretza | 2020-03-22 | 4 | -1/+91 | |
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index : iCE40/ghdl-yosys-plugin | |
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