| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | netlists-inference: handle multiple dff with the same clock. Fix #1563 | Tristan Gingold | 2021-01-01 | 1 | -0/+2 |
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| * | synth: fix handling of multi-dim ROM. Fix #1390 | Tristan Gingold | 2020-07-24 | 1 | -0/+9 |
| | | | | | Document index order for memidx. | ||||
| * | netlists-gates.ads: add comments. | Tristan Gingold | 2020-06-02 | 1 | -6/+8 |
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| * | synth: handle reduction operators. Fix #1342 | Tristan Gingold | 2020-05-27 | 1 | -8/+9 |
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| * | synth: handle initialized inout port. For #1312 | Tristan Gingold | 2020-05-15 | 1 | -10/+14 |
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| * | netlists-gates: reserve pmux and latch. | Tristan Gingold | 2020-05-09 | 1 | -51/+60 |
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| * | synth: add Id_Enable gate (for sequential assertions). | Tristan Gingold | 2020-05-06 | 1 | -0/+3 |
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| * | netlists-memories: Handle gated dyn_extract. | Tristan Gingold | 2020-04-26 | 1 | -5/+5 |
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| * | synth: add tri gate. | Tristan Gingold | 2020-04-22 | 1 | -1/+20 |
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| * | synth: rework edge handling to properly support falling edge. Fix #1227 | Tristan Gingold | 2020-04-15 | 1 | -8/+9 |
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| * | synth: preliminary support of multiport rams (using shared variable). | Tristan Gingold | 2020-03-28 | 1 | -0/+3 |
| | | | | | For #1069 | ||||
| * | netlists-gates: improve comments. | Tristan Gingold | 2020-03-26 | 1 | -1/+4 |
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| * | synth: add id_inout gate to handle inout behaviour. Fir #1166 | Tristan Gingold | 2020-03-23 | 1 | -0/+12 |
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| * | synth-disp_vhdl: do not wrap inout ports. For #1166 | Tristan Gingold | 2020-03-22 | 1 | -0/+1 |
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| * | netlists: add id_nop gate. | Tristan Gingold | 2020-03-22 | 1 | -0/+3 |
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| * | synth: handle numeric_std minimum/maximum. Fix #1168 | Tristan Gingold | 2020-03-21 | 1 | -44/+48 |
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| * | synthesis: handle initialized output ports. | Tristan Gingold | 2020-03-07 | 1 | -7/+9 |
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| * | netlists: add midff | Tristan Gingold | 2020-02-20 | 1 | -0/+8 |
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| * | synth: add mdff. | Tristan Gingold | 2020-02-17 | 1 | -0/+8 |
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| * | synth: add id_abs gate. For #1101 | Tristan Gingold | 2020-01-20 | 1 | -10/+11 |
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| * | netlists-disp_vhdl: display iadff. | Tristan Gingold | 2019-12-31 | 1 | -6/+13 |
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| * | synth: add minor comments. | Tristan Gingold | 2019-12-23 | 1 | -0/+2 |
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| * | synth: add Get_Input_Instance. | Tristan Gingold | 2019-12-14 | 1 | -0/+2 |
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| * | netlists-gates: add comments. | Tristan Gingold | 2019-12-05 | 1 | -3/+13 |
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| * | netlists-gates: add comments. | Tristan Gingold | 2019-11-11 | 1 | -0/+3 |
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| * | netlists: add more support for dyn_insert_en | Tristan Gingold | 2019-11-11 | 1 | -0/+3 |
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| * | netlists: add dyn_insert_en gate. | Tristan Gingold | 2019-11-11 | 1 | -17/+21 |
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| * | netlists-expands: expand dyn_insert | Tristan Gingold | 2019-11-01 | 1 | -0/+3 |
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| * | netlists: add formal input gates. | Tristan Gingold | 2019-10-30 | 1 | -0/+8 |
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| * | synth: generate cover for assertion precedent. | Tristan Gingold | 2019-10-21 | 1 | -0/+4 |
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| * | synth: add netlists-memories to extract memories. Still WIP. | Tristan Gingold | 2019-10-17 | 1 | -0/+1 |
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| * | netlists: declare memory gates. | Tristan Gingold | 2019-10-15 | 1 | -0/+36 |
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| * | netlists: rename id_memidx1 to id_memidx | Tristan Gingold | 2019-10-03 | 1 | -1/+1 |
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| * | synth: replace memidx2 by addidx; handle some 2d arrays. | Tristan Gingold | 2019-10-03 | 1 | -2/+2 |
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| * | synth: simplify dyn_insert. | Tristan Gingold | 2019-10-02 | 1 | -1/+1 |
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| * | synth: simplify id_dyn_extract. | Tristan Gingold | 2019-10-02 | 1 | -1/+1 |
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| * | synth: introduce memidx1 | Tristan Gingold | 2019-10-02 | 1 | -1/+1 |
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| * | netlists: add memidx1 and memidx2 gates. | Tristan Gingold | 2019-10-02 | 1 | -4/+10 |
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| * | netlists-disp_vhdl: handle Const_Log, add comments, fix assertion. | Tristan Gingold | 2019-10-02 | 1 | -0/+3 |
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| * | synth: add support for integer rem. | Tristan Gingold | 2019-10-01 | 1 | -1/+2 |
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| * | synth: improve support of * and /. Fix #953 | Tristan Gingold | 2019-09-30 | 1 | -2/+4 |
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| * | synth: add support for mod operator. | Tristan Gingold | 2019-09-28 | 1 | -20/+22 |
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| * | synth: handle rotate. | Tristan Gingold | 2019-09-22 | 1 | -26/+34 |
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| * | synth: use constant for constant values. | Tristan Gingold | 2019-09-21 | 1 | -0/+2 |
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| * | synth: Add support for PSL cover directive (#930) | T. Meissner | 2019-09-19 | 1 | -0/+1 |
| | | | | | | | * synth: Add support for PSL cover directive * testsuite/synth: Add tests for PSL cover directives | ||||
| * | synth-inference: detect false loop. | Tristan Gingold | 2019-09-17 | 1 | -0/+2 |
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| * | synth: minor refactoring about const gates. | Tristan Gingold | 2019-09-15 | 1 | -0/+9 |
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| * | synth: handle unsigned shift left. | Tristan Gingold | 2019-09-11 | 1 | -53/+57 |
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| * | synth: add const_x gate. | Tristan Gingold | 2019-09-11 | 1 | -0/+1 |
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| * | synth: add const_sb32, add smul/umul. | Tristan Gingold | 2019-09-07 | 1 | -2/+4 |
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index : iCE40/ghdl | |
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