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path: root/techlibs/xilinx/abc_unmap.v
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* Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-041-211/+0
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* Add (* techmap_autopurge *) to abc_unmap.v tooEddie Hung2019-09-231-11/+11
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* Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect"Eddie Hung2019-09-231-38/+38
| | | | This reverts commit 67c2db3486a7b2ff34f89dc861fb66d51ba6101b.
* Remove (* techmap_autopurge *) from abc_unmap.v since no effectEddie Hung2019-09-231-38/+38
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* $__ABC_REG to have WIDTH parameterEddie Hung2019-09-191-1/+2
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* Fix DSP48E1 timing by breaking P path if MREG or PREGEddie Hung2019-09-191-2/+4
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* Revert "Different approach to timing"Eddie Hung2019-09-191-2/+2
| | | | This reverts commit 41256f48a5f3231e231cbdf9380a26128f272044.
* Different approach to timingEddie Hung2019-09-191-2/+2
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* Use (* techmap_autopurge *) to suppress techmap warningsEddie Hung2019-09-191-39/+44
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* Add no MULT no DPORT configEddie Hung2019-09-131-2/+2
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* Add support for MULT and DPORTEddie Hung2019-09-131-5/+4
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* Initial DSP48E1 box supportEddie Hung2019-09-121-0/+176
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* xilinx to use abc_map.v with -max_iter 1Eddie Hung2019-08-201-94/+2
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* Remove sequential extensionEddie Hung2019-08-201-119/+0
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* Wrap SRL{16,32} tooEddie Hung2019-08-201-1/+36
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* Wrap LUTRAMs in order to capture comb/seq behaviourEddie Hung2019-08-201-0/+64
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* Use abc_{map,unmap,model}.vEddie Hung2019-08-201-0/+140