iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Revert "Add shregmap -init_msb_first and use in synth_xilinx"	Eddie Hung	2019-03-14	1	-3/+2
*	Merge remote-tracking branch 'origin/master' into xc7srl	Eddie Hung	2019-03-14	1	-16/+54
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\| *	Merge pull request #842 from litghost/merge_upstream	Clifford Wolf	2019-03-05	1	-16/+52
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\| \| *	Use singular for disabling of DRAM or BRAM inference.	Keith Rothman	2019-03-01	1	-13/+13
\| \| *	Modify arguments to match existing style.	Keith Rothman	2019-03-01	1	-6/+6
\| \| *	Changes required for VPR place and route synth_xilinx.	Keith Rothman	2019-03-01	1	-16/+52
\| * \|	Use "write_edif -pvector bra" for Xilinx EDIF files	Clifford Wolf	2019-03-05	1	-1/+1
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* \|	Add shregmap -init_msb_first and use in synth_xilinx	Eddie Hung	2019-03-14	1	-2/+2
* \|	Move shregmap until after first techmap	Eddie Hung	2019-03-13	1	-2/+2
* \|	synth_xilinx to call shregmap with enable support	Eddie Hung	2019-02-28	1	-1/+1
* \|	synth_xilinx to use shregmap with -params too	Eddie Hung	2019-02-28	1	-1/+1
* \|	synth_xilinx to now have shregmap call after dff2dffe	Eddie Hung	2019-02-28	1	-0/+2
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*	Fix typographical and grammatical errors and inconsistencies.	whitequark	2019-01-02	1	-1/+1
*	xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.	Tim 'mithro' Ansell	2018-10-08	1	-3/+2
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
*	Improving vpr output support.	Tim 'mithro' Ansell	2018-04-18	1	-3/+34
*	Add Xilinx RAM64X1D and RAM128X1D simulation models	Clifford Wolf	2018-03-07	1	-2/+0
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
*	Added black box modules for all the 7-series design elements (as listed in ug...	Clifford Wolf	2016-03-19	1	-0/+2
*	Run dffsr2dff in synth_xilinx	Clifford Wolf	2016-02-13	1	-0/+2
*	Added "abc -luts" option, Improved Xilinx logic mapping	Clifford Wolf	2016-02-01	1	-2/+2
*	Bugfix in Xilinx LUT mapping	Clifford Wolf	2015-10-30	1	-1/+1
*	Added read-enable to memory model	Clifford Wolf	2015-09-25	1	-2/+2
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-3/+3
*	Added output args to synth_ice40	Clifford Wolf	2015-05-26	1	-2/+2
*	Towards DRAM support in Xilinx flow	Clifford Wolf	2015-04-09	1	-0/+12
*	Added Xilinx bram black-box modules	Clifford Wolf	2015-04-06	1	-0/+2
*	Added "dffinit", Support for initialized Xilinx DFF	Clifford Wolf	2015-04-04	1	-5/+6
*	Added "stat" to "synth" and "synth_xilinx"	Clifford Wolf	2015-02-15	1	-0/+2
*	Added final checks to "synth" and "synth_xilinx"	Clifford Wolf	2015-02-15	1	-0/+10
*	no support for 6-series xilinx devices	Clifford Wolf	2015-02-01	1	-1/+1
*	Added Xilinx example for Basys3 board	Clifford Wolf	2015-02-01	1	-0/+2
*	Various cleanups in xilinx techlib	Clifford Wolf	2015-01-18	1	-6/+6
*	Added synth_xilinx -retime -flatten	Clifford Wolf	2015-01-17	1	-2/+28
*	Added MUXCY and XORCY support to synth_xilinx	Clifford Wolf	2015-01-17	1	-2/+10
*	Added dff2dffe to synth_xilinx	Clifford Wolf	2015-01-16	1	-0/+2
*	Added Xilinx MUXF7 and MUXF8 support	Clifford Wolf	2015-01-15	1	-2/+2
*	Various cleanups in synth_xilinx command	Clifford Wolf	2015-01-13	1	-54/+8
*	Various small improvements to synth_xilinx	Clifford Wolf	2015-01-06	1	-8/+6
*	Towards Xilinx bram support	Clifford Wolf	2015-01-05	1	-16/+20
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-1/+5
*	Added "techmap -share_map" option	Clifford Wolf	2013-11-24	1	-4/+4
*	Added synth_xilinx command	Clifford Wolf	2013-10-27	1	-0/+210